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ASoC: amd: acp: refactor acp i2s clock generation code
Refactor acp i2s LRCLK,BCLK generation code and move to commnon file. Signed-off-by: Syed Saba Kareem <Syed.SabaKareem@amd.com> Link: https://lore.kernel.org/r/20231021145110.478744-2-Syed.SabaKareem@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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33d120a49b
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2 changed files with 32 additions and 39 deletions
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@ -20,10 +20,42 @@
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitfield.h>
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#include "amd.h"
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#define DRV_NAME "acp_i2s_playcap"
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#define I2S_MASTER_MODE_ENABLE 1
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#define I2S_MODE_ENABLE 0
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#define I2S_FORMAT_MODE GENMASK(1, 1)
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#define LRCLK_DIV_FIELD GENMASK(10, 2)
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#define BCLK_DIV_FIELD GENMASK(23, 11)
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static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
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{
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u32 i2s_clk_reg, val;
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switch (dai_id) {
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case I2S_SP_INSTANCE:
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i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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case I2S_BT_INSTANCE:
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i2s_clk_reg = ACP_I2STDM1_MSTRCLKGEN;
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break;
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case I2S_HS_INSTANCE:
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i2s_clk_reg = ACP_I2STDM2_MSTRCLKGEN;
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break;
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default:
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i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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}
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val = I2S_MASTER_MODE_ENABLE;
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val |= I2S_MODE_ENABLE & BIT(1);
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val |= FIELD_PREP(LRCLK_DIV_FIELD, adata->lrclk_div);
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val |= FIELD_PREP(BCLK_DIV_FIELD, adata->bclk_div);
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writel(val, adata->acp_base + i2s_clk_reg);
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}
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static int acp_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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@ -188,17 +188,6 @@ struct acp_dev_data {
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u32 xfer_rx_resolution[3];
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};
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union acp_i2stdm_mstrclkgen {
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struct {
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u32 i2stdm_master_mode : 1;
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u32 i2stdm_format_mode : 1;
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u32 i2stdm_lrclk_div_val : 9;
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u32 i2stdm_bclk_div_val : 11;
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u32:10;
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} bitfields, bits;
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u32 u32_all;
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};
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extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
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extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
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@ -276,32 +265,4 @@ static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int
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POINTER_RETURN_BYTES:
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return byte_count;
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}
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static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
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{
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union acp_i2stdm_mstrclkgen mclkgen;
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u32 master_reg;
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switch (dai_id) {
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case I2S_SP_INSTANCE:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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case I2S_BT_INSTANCE:
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master_reg = ACP_I2STDM1_MSTRCLKGEN;
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break;
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case I2S_HS_INSTANCE:
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master_reg = ACP_I2STDM2_MSTRCLKGEN;
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break;
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default:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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}
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mclkgen.bits.i2stdm_master_mode = 0x1;
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mclkgen.bits.i2stdm_format_mode = 0x00;
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mclkgen.bits.i2stdm_bclk_div_val = adata->bclk_div;
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mclkgen.bits.i2stdm_lrclk_div_val = adata->lrclk_div;
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writel(mclkgen.u32_all, adata->acp_base + master_reg);
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}
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#endif
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