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drm/msm/dpu: move max clock decision to dpu_kms.

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dpu_core_perf should not make decisions on the maximum possible core
clock rate. Pass the value from dpu_kms_hw_init() and drop handling of
core_clk from dpu_core_perf.c

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550201/
Link: https://lore.kernel.org/r/20230730010102.350713-10-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2023-07-30 04:01:01 +03:00
parent d64d83806a
commit 4161ec7e93
3 changed files with 15 additions and 17 deletions
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11
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
View file

@ -489,21 +489,14 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf)
}
perf->max_core_clk_rate = 0;
perf->core_clk = NULL;
}
int dpu_core_perf_init(struct dpu_core_perf *perf,
const struct dpu_perf_cfg *perf_cfg,
struct clk *core_clk)
unsigned long max_core_clk_rate)
{
perf->perf_cfg = perf_cfg;
perf->core_clk = core_clk;
perf->max_core_clk_rate = clk_get_rate(core_clk);
if (!perf->max_core_clk_rate) {
DPU_DEBUG("optional max core clk rate, use default\n");
perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
}
perf->max_core_clk_rate = max_core_clk_rate;
return 0;
}

8
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
View file

@ -12,8 +12,6 @@
#include "dpu_hw_catalog.h"
#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
/**
* struct dpu_core_perf_params - definition of performance parameters
* @max_per_pipe_ib: maximum instantaneous bandwidth request
@ -37,7 +35,6 @@ struct dpu_core_perf_tune {
/**
* struct dpu_core_perf - definition of core performance context
* @perf_cfg: Platform-specific performance configuration
* @core_clk: Pointer to the core clock
* @core_clk_rate: current core clock rate
* @max_core_clk_rate: maximum allowable core clock rate
* @perf_tune: debug control for performance tuning
@ -48,7 +45,6 @@ struct dpu_core_perf_tune {
*/
struct dpu_core_perf {
const struct dpu_perf_cfg *perf_cfg;
struct clk *core_clk;
u64 core_clk_rate;
u64 max_core_clk_rate;
struct dpu_core_perf_tune perf_tune;
@ -92,11 +88,11 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf);
* dpu_core_perf_init - initialize the given core performance context
* @perf: Pointer to core performance context
* @perf_cfg: Pointer to platform performance configuration
* @core_clk: pointer to core clock
* @max_core_clk_rate: Maximum core clock rate
*/
int dpu_core_perf_init(struct dpu_core_perf *perf,
const struct dpu_perf_cfg *perf_cfg,
struct clk *core_clk);
unsigned long max_core_clk_rate);
struct dpu_kms;

13
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View file

@ -1052,11 +1052,14 @@ unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
return clk_get_rate(clk);
}
#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
static int dpu_kms_hw_init(struct msm_kms *kms)
{
struct dpu_kms *dpu_kms;
struct drm_device *dev;
int i, rc = -EINVAL;
unsigned long max_core_clk_rate;
u32 core_rev;
if (!kms) {
@ -1170,8 +1173,14 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
dpu_kms->hw_vbif[vbif->id] = hw;
}
rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf,
msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core"));
/* TODO: use the same max_freq as in dpu_kms_hw_init */
max_core_clk_rate = dpu_kms_get_clk_rate(dpu_kms, "core");
if (!max_core_clk_rate) {
DPU_DEBUG("max core clk rate not determined, using default\n");
max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE;
}
rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate);
if (rc) {
DPU_ERROR("failed to init perf %d\n", rc);
goto perf_err;