mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-26 04:16:39 +00:00
clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
[ Upstream commitaa690050c0
] Without the SGM_REG_SEL clock enabled the cpu freezes if trying to access registers used by MT7981 clock drivers itself. Mark SGM_REG_SEL as critical to make sure it is always enabled to prevent freezes on boot even if the Ethernet driver which prepares and enables the clock is not loaded or probed at a later point. Fixes:813c3b53b5
("clk: mediatek: add MT7981 clock support") Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/fc157139e6b7f8dfb6430ac7191ba754027705e8.1708221995.git.daniel@makrotopia.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
3c9b19c068
commit
416d67e94e
1 changed files with 3 additions and 2 deletions
|
@ -357,8 +357,9 @@ static const struct mtk_mux top_muxes[] = {
|
|||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
|
||||
sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
|
||||
0x1C0, 21),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
|
||||
0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
|
||||
0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
|
||||
0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
|
||||
/* CLK_CFG_6 */
|
||||
|
|
Loading…
Reference in a new issue