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drm/radeon/kms: fix typo in read_disabled vbios code
BUS_CNTL reg and bits moved between pre-PCIE and PCIE asics. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
e22e6d2070
commit
4171424e66
2 changed files with 17 additions and 6 deletions
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@ -331,7 +331,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
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seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
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viph_control = RREG32(RADEON_VIPH_CONTROL);
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bus_cntl = RREG32(RADEON_BUS_CNTL);
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bus_cntl = RREG32(RV370_BUS_CNTL);
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d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
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d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
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vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
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@ -350,7 +350,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
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WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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/* enable the rom */
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WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
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/* Disable VGA mode */
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WREG32(AVIVO_D1VGA_CONTROL,
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@ -367,7 +367,7 @@ static bool avivo_read_disabled_bios(struct radeon_device *rdev)
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/* restore regs */
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WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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WREG32(RADEON_VIPH_CONTROL, viph_control);
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WREG32(RADEON_BUS_CNTL, bus_cntl);
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WREG32(RV370_BUS_CNTL, bus_cntl);
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WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
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WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
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WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
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@ -390,7 +390,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
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seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
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viph_control = RREG32(RADEON_VIPH_CONTROL);
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bus_cntl = RREG32(RADEON_BUS_CNTL);
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if (rdev->flags & RADEON_IS_PCIE)
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bus_cntl = RREG32(RV370_BUS_CNTL);
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else
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bus_cntl = RREG32(RADEON_BUS_CNTL);
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crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
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crtc2_gen_cntl = 0;
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crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
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@ -412,7 +415,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
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WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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/* enable the rom */
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WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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if (rdev->flags & RADEON_IS_PCIE)
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WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
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else
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WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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/* Turn off mem requests and CRTC for both controllers */
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WREG32(RADEON_CRTC_GEN_CNTL,
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@ -439,7 +445,10 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
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/* restore regs */
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WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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WREG32(RADEON_VIPH_CONTROL, viph_control);
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WREG32(RADEON_BUS_CNTL, bus_cntl);
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if (rdev->flags & RADEON_IS_PCIE)
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WREG32(RV370_BUS_CNTL, bus_cntl);
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else
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WREG32(RADEON_BUS_CNTL, bus_cntl);
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WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
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if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
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WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
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@ -300,6 +300,8 @@
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# define RADEON_BUS_READ_BURST (1 << 30)
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#define RADEON_BUS_CNTL1 0x0034
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# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
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#define RV370_BUS_CNTL 0x004c
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# define RV370_BUS_BIOS_DIS_ROM (1 << 2)
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/* rv370/rv380, rv410, r423/r430/r480, r5xx */
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#define RADEON_MSI_REARM_EN 0x0160
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# define RV370_MSI_REARM_EN (1 << 0)
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