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tg3: Fix read DMA FIFO overruns on recent devices
Earlier versions of tg3 devices had a problem where the read DMA FIFO could be overrun in certain edge conditions. The fix was to limit the number of rx BDs the hardware would fetch at a time. For later devices (5761, 5784 and later ASIC revs), there is a hardware fix that must be enabled to fix the same problem. This patch adds that hardware fix. There is a gap in the ASIC revision lineage where neither fix is applied. This is intentional as these ASIC revisions are not afflicted by the bug. Reviewed-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2 changed files with 15 additions and 1 deletions
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@ -8015,6 +8015,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
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(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
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val = tr32(TG3_RDMA_RSRVCTRL_REG);
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tw32(TG3_RDMA_RSRVCTRL_REG,
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val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
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}
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/* Receive/send statistics. */
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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val = tr32(RCVLPC_STATS_ENABLE);
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@ -1302,7 +1302,11 @@
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#define RDMAC_STATUS_FIFOURUN 0x00000080
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#define RDMAC_STATUS_FIFOOREAD 0x00000100
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#define RDMAC_STATUS_LNGREAD 0x00000200
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/* 0x4808 --> 0x4c00 unused */
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/* 0x4808 --> 0x4900 unused */
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#define TG3_RDMA_RSRVCTRL_REG 0x00004900
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#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
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/* 0x4904 --> 0x4c00 unused */
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/* Write DMA control registers */
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#define WDMAC_MODE 0x00004c00
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