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mmc: dw_mmc: support DDR mode
This patch adds DDR mode support to dw_mmc. If we set any bit in UHS_REG bit[16:31], the card of that slot is supported for DDR mode. For example, if UHS_REG[16] is set, card number 0 is DDR mode. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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parent
e7054ba1f7
commit
41babf753c
2 changed files with 9 additions and 1 deletions
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@ -662,6 +662,7 @@ static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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{
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struct dw_mci_slot *slot = mmc_priv(mmc);
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struct dw_mci_slot *slot = mmc_priv(mmc);
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u32 regs;
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/* set default 1 bit mode */
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/* set default 1 bit mode */
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slot->ctype = SDMMC_CTYPE_1BIT;
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slot->ctype = SDMMC_CTYPE_1BIT;
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@ -678,6 +679,13 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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break;
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break;
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}
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}
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/* DDR mode set */
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if (ios->ddr) {
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regs = mci_readl(slot->host, UHS_REG);
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regs |= (0x1 << slot->id) << 16;
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mci_writel(slot->host, UHS_REG, regs);
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}
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if (ios->clock) {
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if (ios->clock) {
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/*
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/*
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* Use mirror of ios->clock to prevent race with mmc
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* Use mirror of ios->clock to prevent race with mmc
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@ -43,6 +43,7 @@
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#define SDMMC_USRID 0x068
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#define SDMMC_USRID 0x068
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#define SDMMC_VERID 0x06c
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#define SDMMC_VERID 0x06c
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#define SDMMC_HCON 0x070
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#define SDMMC_HCON 0x070
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#define SDMMC_UHS_REG 0x074
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#define SDMMC_BMOD 0x080
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#define SDMMC_BMOD 0x080
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#define SDMMC_PLDMND 0x084
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#define SDMMC_PLDMND 0x084
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#define SDMMC_DBADDR 0x088
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#define SDMMC_DBADDR 0x088
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@ -51,7 +52,6 @@
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#define SDMMC_DSCADDR 0x094
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#define SDMMC_DSCADDR 0x094
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_DATA 0x100
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#define SDMMC_DATA 0x100
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#define SDMMC_DATA_ADR 0x100
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/* shift bit field */
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/* shift bit field */
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#define _SBF(f, v) ((v) << (f))
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#define _SBF(f, v) ((v) << (f))
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