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clk: renesas: rcar-gen3: Add Z2 clock divider support
This patch adds Z2 clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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parent
3391891fa9
commit
41ceeb5fef
2 changed files with 17 additions and 6 deletions
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@ -63,7 +63,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
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}
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/*
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* Z Clock
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* Z Clock & Z2 Clock
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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@ -75,11 +75,13 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
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#define CPG_FRQCRB_KICK BIT(31)
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#define CPG_FRQCRC 0x000000e0
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#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
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#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
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struct cpg_z_clk {
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struct clk_hw hw;
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void __iomem *reg;
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void __iomem *kick_reg;
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unsigned long mask;
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};
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#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
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@ -89,8 +91,10 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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u32 val;
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mult = 32 - FIELD_GET(CPG_FRQCRC_ZFC_MASK, clk_readl(zclk->reg));
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val = clk_readl(zclk->reg) & zclk->mask;
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mult = 32 - (val >> __ffs(zclk->mask));
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/* Factor of 2 is for fixed divider */
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return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
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@ -124,8 +128,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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val = clk_readl(zclk->reg) & ~CPG_FRQCRC_ZFC_MASK;
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val |= FIELD_PREP(CPG_FRQCRC_ZFC_MASK, 32 - mult);
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val = clk_readl(zclk->reg) & ~zclk->mask;
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val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
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clk_writel(val, zclk->reg);
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/*
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@ -163,7 +167,8 @@ static const struct clk_ops cpg_z_clk_ops = {
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static struct clk * __init cpg_z_clk_register(const char *name,
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const char *parent_name,
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void __iomem *reg)
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void __iomem *reg,
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unsigned long mask)
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{
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struct clk_init_data init;
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struct cpg_z_clk *zclk;
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@ -182,6 +187,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
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zclk->reg = reg + CPG_FRQCRC;
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zclk->kick_reg = reg + CPG_FRQCRB;
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zclk->hw.init = &init;
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zclk->mask = mask;
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clk = clk_register(NULL, &zclk->hw);
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if (IS_ERR(clk))
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@ -551,7 +557,11 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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case CLK_TYPE_GEN3_Z:
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return cpg_z_clk_register(core->name, __clk_get_name(parent),
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base);
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base, CPG_FRQCRC_ZFC_MASK);
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case CLK_TYPE_GEN3_Z2:
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return cpg_z_clk_register(core->name, __clk_get_name(parent),
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base, CPG_FRQCRC_Z2FC_MASK);
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default:
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return ERR_PTR(-EINVAL);
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@ -22,6 +22,7 @@ enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_R,
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CLK_TYPE_GEN3_PE,
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CLK_TYPE_GEN3_Z,
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CLK_TYPE_GEN3_Z2,
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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