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drm/i915: Wrap around the tail offset before setting ring->tail
The HW only accepts offsets within ring->size, and fails peculiarly if the RING_HEAD or RING_TAIL is set to ring->size. Therefore whenever we set ring->head/ring->tail we want to make sure it is within value (using intel_ring_wrap()). v2: Double check execlists as well v3: Remove redundancy with assert_ring_tail_valid() v4: Just assert in intel_ring_reset() rather than be over-defensive. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20180611110845.31890-2-chris@chris-wilson.co.uk
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3 changed files with 24 additions and 8 deletions
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@ -1414,6 +1414,7 @@ __execlists_context_pin(struct intel_engine_cs *engine,
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ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
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ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
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i915_ggtt_offset(ce->ring->vma);
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GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
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ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
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ce->state->obj->pin_global++;
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@ -2002,9 +2003,10 @@ static void execlists_reset(struct intel_engine_cs *engine,
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/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
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regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
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regs[CTX_RING_HEAD + 1] = request->postfix;
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request->ring->head = request->postfix;
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request->ring->head = intel_ring_wrap(request->ring, request->postfix);
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regs[CTX_RING_HEAD + 1] = request->ring->head;
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intel_ring_update_space(request->ring);
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/* Reset WaIdleLiteRestore:bdw,skl as well */
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@ -496,6 +496,10 @@ static int init_ring_common(struct intel_engine_cs *engine)
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DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
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engine->name, I915_READ_HEAD(engine));
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/* Check that the ring offsets point within the ring! */
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GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
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GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
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intel_ring_update_space(ring);
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I915_WRITE_HEAD(engine, ring->head);
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I915_WRITE_TAIL(engine, ring->tail);
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@ -1062,6 +1066,8 @@ int intel_ring_pin(struct intel_ring *ring,
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void intel_ring_reset(struct intel_ring *ring, u32 tail)
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{
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GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
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ring->tail = tail;
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ring->head = tail;
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ring->emit = tail;
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@ -805,6 +805,19 @@ static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
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return pos & (ring->size - 1);
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}
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static inline bool
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intel_ring_offset_valid(const struct intel_ring *ring,
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unsigned int pos)
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{
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if (pos & -ring->size) /* must be strictly within the ring */
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return false;
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if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
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return false;
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return true;
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}
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static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
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{
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/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
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@ -816,12 +829,7 @@ static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
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static inline void
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assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
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{
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/* We could combine these into a single tail operation, but keeping
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* them as seperate tests will help identify the cause should one
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* ever fire.
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*/
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GEM_BUG_ON(!IS_ALIGNED(tail, 8));
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GEM_BUG_ON(tail >= ring->size);
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GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
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/*
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* "Ring Buffer Use"
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