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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip 

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, AMD: Set ARAT feature on AMD processors
  x86, quirk: Fix SB600 revision check
  x86: stop_machine_text_poke() should issue sync_core()
  x86, amd-nb: Misc cleanliness fixes
This commit is contained in:
Linus Torvalds 2011-03-16 10:14:56 -07:00
parent e7fd3b4669 344c21c322
commit 41e0e0738c
5 changed files with 32 additions and 16 deletions
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12
arch/x86/include/asm/amd_nb.h
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@ -13,7 +13,7 @@ extern const struct pci_device_id amd_nb_misc_ids[];
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
struct bootnode; struct bootnode;
extern int early_is_amd_nb(u32 value); extern bool early_is_amd_nb(u32 value);
extern int amd_cache_northbridges(void); extern int amd_cache_northbridges(void);
extern void amd_flush_garts(void); extern void amd_flush_garts(void);
extern int amd_numa_init(void); extern int amd_numa_init(void);
@ -32,18 +32,18 @@ struct amd_northbridge_info {
}; };
extern struct amd_northbridge_info amd_northbridges; extern struct amd_northbridge_info amd_northbridges;
#define AMD_NB_GART 0x1 #define AMD_NB_GART BIT(0)
#define AMD_NB_L3_INDEX_DISABLE 0x2 #define AMD_NB_L3_INDEX_DISABLE BIT(1)
#define AMD_NB_L3_PARTITIONING 0x4 #define AMD_NB_L3_PARTITIONING BIT(2)
#ifdef CONFIG_AMD_NB #ifdef CONFIG_AMD_NB
static inline int amd_nb_num(void) static inline u16 amd_nb_num(void)
{ {
return amd_northbridges.num; return amd_northbridges.num;
} }
static inline int amd_nb_has_feature(int feature) static inline bool amd_nb_has_feature(unsigned feature)
{ {
return ((amd_northbridges.flags & feature) == feature); return ((amd_northbridges.flags & feature) == feature);
} }

7
arch/x86/kernel/alternative.c
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@ -620,7 +620,12 @@ static int __kprobes stop_machine_text_poke(void *data)
flush_icache_range((unsigned long)p->addr, flush_icache_range((unsigned long)p->addr,
(unsigned long)p->addr + p->len); (unsigned long)p->addr + p->len);
} }
/*
* Intel Archiecture Software Developer's Manual section 7.1.3 specifies
* that a core serializing instruction such as "cpuid" should be
* executed on _each_ core before the new instruction is made visible.
*/
sync_core();
return 0; return 0;
} }

18
arch/x86/kernel/amd_nb.c
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@ -48,7 +48,7 @@ static struct pci_dev *next_northbridge(struct pci_dev *dev,
int amd_cache_northbridges(void) int amd_cache_northbridges(void)
{ {
int i = 0; u16 i = 0;
struct amd_northbridge *nb; struct amd_northbridge *nb;
struct pci_dev *misc, *link; struct pci_dev *misc, *link;
@ -103,9 +103,11 @@ int amd_cache_northbridges(void)
} }
EXPORT_SYMBOL_GPL(amd_cache_northbridges); EXPORT_SYMBOL_GPL(amd_cache_northbridges);
/* Ignores subdevice/subvendor but as far as I can figure out /*
they're useless anyways */ * Ignores subdevice/subvendor but as far as I can figure out
int __init early_is_amd_nb(u32 device) * they're useless anyways
*/
bool __init early_is_amd_nb(u32 device)
{ {
const struct pci_device_id *id; const struct pci_device_id *id;
u32 vendor = device & 0xffff; u32 vendor = device & 0xffff;
@ -113,8 +115,8 @@ int __init early_is_amd_nb(u32 device)
device >>= 16; device >>= 16;
for (id = amd_nb_misc_ids; id->vendor; id++) for (id = amd_nb_misc_ids; id->vendor; id++)
if (vendor == id->vendor && device == id->device) if (vendor == id->vendor && device == id->device)
return 1; return true;
return 0; return false;
} }
int amd_get_subcaches(int cpu) int amd_get_subcaches(int cpu)
@ -176,9 +178,9 @@ int amd_set_subcaches(int cpu, int mask)
return 0; return 0;
} }
int amd_cache_gart(void) static int amd_cache_gart(void)
{ {
int i; u16 i;
if (!amd_nb_has_feature(AMD_NB_GART)) if (!amd_nb_has_feature(AMD_NB_GART))
return 0; return 0;

4
arch/x86/kernel/cpu/amd.c
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@ -611,6 +611,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
} }
} }
#endif #endif
/* As a rule processors have APIC timer running in deep C states */
if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400))
set_cpu_cap(c, X86_FEATURE_ARAT);
} }
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_32

7
arch/x86/kernel/early-quirks.c
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@ -159,7 +159,12 @@ static void __init ati_bugs_contd(int num, int slot, int func)
if (rev >= 0x40) if (rev >= 0x40)
acpi_fix_pin2_polarity = 1; acpi_fix_pin2_polarity = 1;
if (rev > 0x13) /*
* SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
* SB700: revisions 0x39, 0x3a, ...
* SB800: revisions 0x40, 0x41, ...
*/
if (rev >= 0x39)
return; return;
if (acpi_use_timer_override) if (acpi_use_timer_override)