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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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sh-pfc: Move GPIO registers access functions to gpio.c
Move the sh_pfc_setup_data_regs(), sh_pfc_setup_data_reg(), sh_pfc_get_data_reg(), sh_pfc_read_bit() and sh_pfc_write_bit() function to gpio.c as they belong to the GPIO implementation. Inline sh_pfc_read_bit() and sh_pfc_write_bit() in their only call location. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Laurent Pinchart
parent
fd9d05b0fd
commit
41f1219fae
3 changed files with 97 additions and 116 deletions
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@ -55,8 +55,7 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
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return 0;
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}
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static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
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unsigned long address)
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void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address)
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{
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struct sh_pfc_window *window;
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int k;
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@ -111,8 +110,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
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return 1;
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}
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static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width)
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unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width)
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{
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switch (reg_width) {
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case 8:
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@ -127,8 +126,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
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return 0;
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}
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static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width, unsigned long data)
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void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
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unsigned long data)
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{
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switch (reg_width) {
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case 8:
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@ -145,37 +144,6 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
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BUG();
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}
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int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
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{
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unsigned long pos;
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pos = dr->reg_width - (in_pos + 1);
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pr_debug("read_bit: addr = %lx, pos = %ld, "
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"r_width = %ld\n", dr->reg, pos, dr->reg_width);
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return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
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}
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void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
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unsigned long value)
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{
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unsigned long pos;
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pos = dr->reg_width - (in_pos + 1);
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pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
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"r_width = %ld\n",
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dr->reg, !!value, pos, dr->reg_width);
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if (value)
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set_bit(pos, &dr->reg_shadow);
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else
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clear_bit(pos, &dr->reg_shadow);
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sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
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}
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static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
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struct pinmux_cfg_reg *crp,
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unsigned long in_pos,
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@ -242,73 +210,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
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}
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static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
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{
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struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
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struct pinmux_data_reg *data_reg;
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int k, n;
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k = 0;
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while (1) {
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data_reg = pfc->info->data_regs + k;
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if (!data_reg->reg_width)
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break;
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data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
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for (n = 0; n < data_reg->reg_width; n++) {
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if (data_reg->enum_ids[n] == gpiop->enum_id) {
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gpiop->flags &= ~PINMUX_FLAG_DREG;
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gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
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gpiop->flags &= ~PINMUX_FLAG_DBIT;
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gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
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return;
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}
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}
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k++;
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}
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BUG();
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}
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static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
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{
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struct pinmux_data_reg *drp;
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int k;
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for (k = 0; k < pfc->info->nr_pins; k++) {
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if (pfc->info->pins[k].enum_id == 0)
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continue;
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sh_pfc_setup_data_reg(pfc, k);
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}
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k = 0;
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while (1) {
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drp = pfc->info->data_regs + k;
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if (!drp->reg_width)
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break;
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drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
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drp->reg_width);
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k++;
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}
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}
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void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
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struct pinmux_data_reg **drp, int *bitp)
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{
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struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);
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int k, n;
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k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
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n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
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*drp = pfc->info->data_regs + k;
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*bitp = n;
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}
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static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
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struct pinmux_cfg_reg **crp, int *fieldp,
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int *valuep, unsigned long **cntp)
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@ -518,7 +419,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
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spin_lock_init(&pfc->lock);
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pinctrl_provide_dummies();
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sh_pfc_setup_data_regs(pfc);
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/*
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* Initialize pinctrl bindings first
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@ -46,11 +46,12 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
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int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
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int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
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int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
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void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
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unsigned long value);
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void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
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struct pinmux_data_reg **drp, int *bitp);
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void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address);
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unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
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unsigned long reg_width);
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void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
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unsigned long data);
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struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin);
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
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int cfg_mode);
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@ -36,6 +36,71 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
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return gpio_to_pfc_chip(gc)->pfc;
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}
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static void gpio_get_data_reg(struct sh_pfc *pfc, unsigned int gpio,
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struct pinmux_data_reg **dr, unsigned int *bit)
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{
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struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio);
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*dr = pfc->info->data_regs
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+ ((gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT);
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*bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
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}
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static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
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{
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struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
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struct pinmux_data_reg *data_reg;
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int k, n;
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k = 0;
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while (1) {
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data_reg = pfc->info->data_regs + k;
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if (!data_reg->reg_width)
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break;
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data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
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for (n = 0; n < data_reg->reg_width; n++) {
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if (data_reg->enum_ids[n] == gpiop->enum_id) {
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gpiop->flags &= ~PINMUX_FLAG_DREG;
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gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
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gpiop->flags &= ~PINMUX_FLAG_DBIT;
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gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
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return;
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}
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}
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k++;
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}
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BUG();
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}
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static void gpio_setup_data_regs(struct sh_pfc *pfc)
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{
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struct pinmux_data_reg *drp;
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int k;
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for (k = 0; k < pfc->info->nr_pins; k++) {
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if (pfc->info->pins[k].enum_id == 0)
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continue;
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gpio_setup_data_reg(pfc, k);
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}
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k = 0;
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while (1) {
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drp = pfc->info->data_regs + k;
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if (!drp->reg_width)
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break;
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drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
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drp->reg_width);
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k++;
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}
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}
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/* -----------------------------------------------------------------------------
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* Pin GPIOs
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*/
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@ -59,10 +124,19 @@ static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
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static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)
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{
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struct pinmux_data_reg *dr;
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int bit;
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unsigned long pos;
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unsigned int bit;
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sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
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sh_pfc_write_bit(dr, bit, value);
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gpio_get_data_reg(pfc, offset, &dr, &bit);
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pos = dr->reg_width - (bit + 1);
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if (value)
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set_bit(pos, &dr->reg_shadow);
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else
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clear_bit(pos, &dr->reg_shadow);
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sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
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}
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static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
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@ -82,10 +156,14 @@ static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
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{
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struct sh_pfc *pfc = gpio_to_pfc(gc);
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struct pinmux_data_reg *dr;
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int bit;
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unsigned long pos;
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unsigned int bit;
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sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
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return sh_pfc_read_bit(dr, bit);
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gpio_get_data_reg(pfc, offset, &dr, &bit);
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pos = dr->reg_width - (bit + 1);
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return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
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}
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static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
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@ -226,6 +304,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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unsigned int i;
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int ret;
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gpio_setup_data_regs(pfc);
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/* Register the real GPIOs chip. */
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chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
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if (IS_ERR(chip))
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