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r8169: Modify the mothod for PHY settings of RTL8111G
Replace the current settings with rtl_writephy and rtl_readphy. For the hardware, the settings are same with previous ones. This make the setting method like the previous chips. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
0427d0152e
commit
41f44d1389
1 changed files with 31 additions and 21 deletions
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@ -1024,14 +1024,6 @@ static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
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(RTL_R32(GPHY_OCP) & 0xffff) : ~0;
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}
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static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
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{
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int val;
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val = r8168_phy_ocp_read(tp, reg);
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r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
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}
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static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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@ -3370,23 +3362,41 @@ static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
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{
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rtl_apply_firmware(tp);
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if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
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rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
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else
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rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0a46);
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if (rtl_readphy(tp, 0x10) & 0x0100) {
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rtl_writephy(tp, 0x1f, 0x0bcc);
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rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
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} else {
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rtl_writephy(tp, 0x1f, 0x0bcc);
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rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
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}
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if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
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rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
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else
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rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
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rtl_writephy(tp, 0x1f, 0x0a46);
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if (rtl_readphy(tp, 0x13) & 0x0100) {
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rtl_writephy(tp, 0x1f, 0x0c41);
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rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
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} else {
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rtl_writephy(tp, 0x1f, 0x0bcc);
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rtl_w1w0_phy(tp, 0x12, 0x0000, 0x0002);
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}
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rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
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rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
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/* Enable PHY auto speed down */
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rtl_writephy(tp, 0x1f, 0x0a44);
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rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
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r8168_phy_ocp_write(tp, 0xa436, 0x8012);
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rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
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/* EEE auto-fallback function */
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rtl_writephy(tp, 0x1f, 0x0a4b);
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rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
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rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
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/* Enable UC LPF tune function */
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rtl_writephy(tp, 0x1f, 0x0a43);
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rtl_writephy(tp, 0x13, 0x8012);
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rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0c42);
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rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
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rtl_writephy(tp, 0x1f, 0x0000);
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}
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static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
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