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MIPS: Malta: Use generic plat_irq_dispatch
The generic plat_irq_dispatch provided in irq_cpu.c is sufficient for dispatching interrupts on Malta in legacy and vectored interrupt modes. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7821/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -190,92 +190,6 @@ static irqreturn_t corehi_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static inline int clz(unsigned long x)
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{
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__asm__(
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" .set push \n"
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" .set mips32 \n"
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" clz %0, %1 \n"
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" .set pop \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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/*
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* Version of ffs that only looks at bits 12..15.
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*/
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static inline unsigned int irq_ffs(unsigned int pending)
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{
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#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
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return -clz(pending) + 31 - CAUSEB_IP;
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#else
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unsigned int a0 = 7;
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unsigned int t0;
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t0 = pending & 0xf000;
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t0 = t0 < 1;
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t0 = t0 << 2;
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a0 = a0 - t0;
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pending = pending << t0;
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t0 = pending & 0xc000;
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t0 = t0 < 1;
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t0 = t0 << 1;
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a0 = a0 - t0;
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pending = pending << t0;
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t0 = pending & 0x8000;
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t0 = t0 < 1;
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/* t0 = t0 << 2; */
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a0 = a0 - t0;
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/* pending = pending << t0; */
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return a0;
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#endif
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}
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/*
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* IRQs on the Malta board look basically (barring software IRQs which we
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* don't use at all and all external interrupt sources are combined together
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* on hardware interrupt 0 (MIPS IRQ 2)) like:
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Combined hardware interrupt (hw0)
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* 3 Hardware (ignored)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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* 6 Hardware (ignored)
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* 7 R4k timer (what we use)
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Combined hardware interrupt
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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int irq;
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if (unlikely(!pending)) {
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spurious_interrupt();
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return;
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}
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irq = irq_ffs(pending);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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}
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#ifdef CONFIG_MIPS_MT_SMP
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#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
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@ -438,12 +352,6 @@ void __init arch_init_irq(void)
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cpu_ipi_resched_irq = MSC01E_INT_SW0;
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cpu_ipi_call_irq = MSC01E_INT_SW1;
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} else {
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if (cpu_has_vint) {
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set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ,
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ipi_resched_dispatch);
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set_vi_handler (MIPS_CPU_IPI_CALL_IRQ,
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ipi_call_dispatch);
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}
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cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
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MIPS_CPU_IPI_RESCHED_IRQ;
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cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
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