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Two clk driver fixes
- Use devm_kasprintf() to avoid overflows when forming clk names in the Microchip PolarFire driver - Fix the pretty broken Ingenic JZ4760 M/N/OD calculation to actually work and find proper divisors -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmPmy9gRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWtZA//YkdI9ObFNcDIy4hQB1G8ppdwmnwQyUI1 MpTYEKQA1Zuk1HzARcO4WBeGpswKK28gkFgoYuBPvOPsCOgFcb7C9d2sub5rDpKI +rwG4cptgumrYXxwRHx1qiieW65Tl+vqmVDy8fKhtpnFkc2PHbtJDf2FSYgTyMkd MZeqsjcys7kYgRTEBvTo/aG9PeDAzhoAWplFTcLvhnb0MxfzcwSSQp3U8/vOTH+i T1GhWrh5AT0rKEpbuTlc7dodvvs35Y5xkTHRj+wZ63IvCE9/i08k6Jbon2oLsTro Uw7hbfd9WucpKGnjNGXGJLnY3Wg2egx7l6eJaJZiIyRiprEJlAk2j0v1cd9ZrKGD TMwszQuGmD/AzNR+oDzmzcRLIsPFmthfC3YRvwPYC/PpFuiKMeQD0BWkUh9z9c6n AlPlSeNgyWr1nV+mEfoF8X2GsVqlWjvjz1Vc1anAqcfHiL47iSK2ovJN2xfM9kXg rvmSpoNIuFObq525bTUZoQDGqXtB36h1NWuY5PIr9rNdzK+nlVdOp97Yvsl9scJS D8fx5rcF3NlzVgHFa4NEbcJdEdKZVVTmdVHta3rOC0+EMxhLkpaowwaL5Rmgd3mT p3KIzOsVSrL8+J7JyQqPCdEvrODpTyK7PguvicxmyVjFg6CtVeUCj1ucq4IpQV6k GxZrX2A3MJk= =RXcc -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "Two clk driver fixes - Use devm_kasprintf() to avoid overflows when forming clk names in the Microchip PolarFire driver - Fix the pretty broken Ingenic JZ4760 M/N/OD calculation to actually work and find proper divisors" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: ingenic: jz4760: Update M/N/OD calculation algorithm clk: microchip: mpfs-ccc: Use devm_kasprintf() for allocating formatted strings
This commit is contained in:
commit
420b2d431d
2 changed files with 12 additions and 16 deletions
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@ -58,7 +58,7 @@ jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
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unsigned long rate, unsigned long parent_rate,
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unsigned int *pm, unsigned int *pn, unsigned int *pod)
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{
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unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 2;
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unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 1;
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/* The frequency after the N divider must be between 1 and 50 MHz. */
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n = parent_rate / (1 * MHZ);
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@ -66,19 +66,17 @@ jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
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/* The N divider must be >= 2. */
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n = clamp_val(n, 2, 1 << pll_info->n_bits);
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for (;; n >>= 1) {
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od = (unsigned int)-1;
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rate /= MHZ;
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parent_rate /= MHZ;
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do {
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m = (rate / MHZ) * (1 << ++od) * n / (parent_rate / MHZ);
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} while ((m > m_max || m & 1) && (od < 4));
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if (od < 4 && m >= 4 && m <= m_max)
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break;
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for (m = m_max; m >= m_max && n >= 2; n--) {
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m = rate * n / parent_rate;
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od = m & 1;
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m <<= od;
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}
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*pm = m;
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*pn = n;
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*pn = n + 1;
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*pod = 1 << od;
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}
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@ -164,12 +164,11 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_
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for (unsigned int i = 0; i < num_clks; i++) {
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struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
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char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
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char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i);
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if (!name)
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return -ENOMEM;
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snprintf(name, 23, "%s_out%u", parent->name, i);
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out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
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out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
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out_hw->reg_offset;
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@ -201,14 +200,13 @@ static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clo
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for (unsigned int i = 0; i < num_clks; i++) {
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struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
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char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
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if (!name)
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pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u",
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strchrnul(dev->of_node->full_name, '@'), i);
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if (!pll_hw->name)
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return -ENOMEM;
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pll_hw->base = data->pll_base[i];
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snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
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pll_hw->name = (const char *)name;
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pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,
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pll_hw->parents,
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&mpfs_ccc_pll_ops, 0);
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