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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-25 11:55:37 +00:00
net/mlx5: Split irq_pool_affinity logic to new file
The downstream patches add more functionality to irq_pool_affinity. Move the irq_pool_affinity logic to a new file in order to ease the coding and maintenance of it. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Shay Drory
Saeed Mahameed
parent
30c6afa735
commit
424544df97
5 changed files with 157 additions and 97 deletions
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@ -109,7 +109,7 @@ mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/dr_domain.o steering/dr_table.o
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#
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# SF device
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#
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mlx5_core-$(CONFIG_MLX5_SF) += sf/vhca_event.o sf/dev/dev.o sf/dev/driver.o
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mlx5_core-$(CONFIG_MLX5_SF) += sf/vhca_event.o sf/dev/dev.o sf/dev/driver.o irq_affinity.o
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#
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# SF manager
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99
drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
Normal file
99
drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c
Normal file
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@ -0,0 +1,99 @@
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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#include "mlx5_core.h"
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#include "mlx5_irq.h"
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#include "pci_irq.h"
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/* Creating an IRQ from irq_pool */
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static struct mlx5_irq *
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irq_pool_request_irq(struct mlx5_irq_pool *pool, const struct cpumask *req_mask)
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{
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u32 irq_index;
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int err;
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err = xa_alloc(&pool->irqs, &irq_index, NULL, pool->xa_num_irqs,
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GFP_KERNEL);
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if (err)
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return ERR_PTR(err);
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return mlx5_irq_alloc(pool, irq_index, req_mask);
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}
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/* Looking for the IRQ with the smallest refcount and the same mask */
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static struct mlx5_irq *
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irq_pool_find_least_loaded(struct mlx5_irq_pool *pool, const struct cpumask *req_mask)
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{
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int start = pool->xa_num_irqs.min;
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int end = pool->xa_num_irqs.max;
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struct mlx5_irq *irq = NULL;
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struct mlx5_irq *iter;
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int irq_refcount = 0;
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unsigned long index;
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lockdep_assert_held(&pool->lock);
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xa_for_each_range(&pool->irqs, index, iter, start, end) {
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struct cpumask *iter_mask = mlx5_irq_get_affinity_mask(iter);
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int iter_refcount = mlx5_irq_read_locked(iter);
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if (!cpumask_equal(iter_mask, req_mask))
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/* If a user request a mask, skip IRQs that's aren't a match */
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continue;
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if (iter_refcount < pool->min_threshold)
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/* If we found an IRQ with less than min_thres, return it */
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return iter;
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if (!irq || iter_refcount < irq_refcount) {
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/* In case we won't find an IRQ with less than min_thres,
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* keep a pointer to the least used IRQ
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*/
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irq_refcount = iter_refcount;
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irq = iter;
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}
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}
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return irq;
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}
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/**
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* mlx5_irq_affinity_request - request an IRQ according to the given mask.
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* @pool: IRQ pool to request from.
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* @req_mask: cpumask requested for this IRQ.
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*
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* This function returns a pointer to IRQ, or ERR_PTR in case of error.
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*/
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struct mlx5_irq *
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mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, const struct cpumask *req_mask)
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{
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struct mlx5_irq *least_loaded_irq, *new_irq;
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mutex_lock(&pool->lock);
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least_loaded_irq = irq_pool_find_least_loaded(pool, req_mask);
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if (least_loaded_irq &&
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mlx5_irq_read_locked(least_loaded_irq) < pool->min_threshold)
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goto out;
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/* We didn't find an IRQ with less than min_thres, try to allocate a new IRQ */
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new_irq = irq_pool_request_irq(pool, req_mask);
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if (IS_ERR(new_irq)) {
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if (!least_loaded_irq) {
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/* We failed to create an IRQ and we didn't find an IRQ */
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mlx5_core_err(pool->dev, "Didn't find a matching IRQ. err = %ld\n",
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PTR_ERR(new_irq));
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mutex_unlock(&pool->lock);
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return new_irq;
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}
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/* We failed to create a new IRQ for the requested affinity,
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* sharing existing IRQ.
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*/
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goto out;
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}
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least_loaded_irq = new_irq;
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goto unlock;
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out:
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mlx5_irq_get_locked(least_loaded_irq);
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if (mlx5_irq_read_locked(least_loaded_irq) > pool->max_threshold)
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mlx5_core_dbg(pool->dev, "IRQ %u overloaded, pool_name: %s, %u EQs on this irq\n",
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pci_irq_vector(pool->dev->pdev,
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mlx5_irq_get_index(least_loaded_irq)), pool->name,
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mlx5_irq_read_locked(least_loaded_irq) / MLX5_EQ_REFS_PER_IRQ);
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unlock:
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mutex_unlock(&pool->lock);
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return least_loaded_irq;
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}
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@ -31,4 +31,15 @@ int mlx5_irq_detach_nb(struct mlx5_irq *irq, struct notifier_block *nb);
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struct cpumask *mlx5_irq_get_affinity_mask(struct mlx5_irq *irq);
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int mlx5_irq_get_index(struct mlx5_irq *irq);
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struct mlx5_irq_pool;
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#ifdef CONFIG_MLX5_SF
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struct mlx5_irq *mlx5_irq_affinity_request(struct mlx5_irq_pool *pool,
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const struct cpumask *req_mask);
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#else
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static inline struct mlx5_irq *
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mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, const struct cpumask *req_mask)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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#endif
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#endif /* __MLX5_IRQ_H__ */
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@ -7,15 +7,12 @@
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#include <linux/mlx5/driver.h>
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#include "mlx5_core.h"
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#include "mlx5_irq.h"
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#include "pci_irq.h"
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#include "lib/sf.h"
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#ifdef CONFIG_RFS_ACCEL
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#include <linux/cpu_rmap.h>
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#endif
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#define MLX5_MAX_IRQ_NAME (32)
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/* max irq_index is 2047, so four chars */
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#define MLX5_MAX_IRQ_IDX_CHARS (4)
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#define MLX5_SFS_PER_CTRL_IRQ 64
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#define MLX5_IRQ_CTRL_SF_MAX 8
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/* min num of vectors for SFs to be enabled */
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@ -25,7 +22,6 @@
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#define MLX5_EQ_SHARE_IRQ_MAX_CTRL (UINT_MAX)
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#define MLX5_EQ_SHARE_IRQ_MIN_COMP (1)
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#define MLX5_EQ_SHARE_IRQ_MIN_CTRL (4)
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#define MLX5_EQ_REFS_PER_IRQ (2)
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struct mlx5_irq {
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struct atomic_notifier_head nh;
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@ -37,16 +33,6 @@ struct mlx5_irq {
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int irqn;
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};
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struct mlx5_irq_pool {
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char name[MLX5_MAX_IRQ_NAME - MLX5_MAX_IRQ_IDX_CHARS];
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struct xa_limit xa_num_irqs;
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struct mutex lock; /* sync IRQs creations */
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struct xarray irqs;
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u32 max_threshold;
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u32 min_threshold;
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struct mlx5_core_dev *dev;
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};
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struct mlx5_irq_table {
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struct mlx5_irq_pool *pf_pool;
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struct mlx5_irq_pool *sf_ctrl_pool;
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@ -164,7 +150,13 @@ static void irq_put(struct mlx5_irq *irq)
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mutex_unlock(&pool->lock);
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}
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static int irq_get_locked(struct mlx5_irq *irq)
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int mlx5_irq_read_locked(struct mlx5_irq *irq)
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{
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lockdep_assert_held(&irq->pool->lock);
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return irq->refcount;
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}
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int mlx5_irq_get_locked(struct mlx5_irq *irq)
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{
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lockdep_assert_held(&irq->pool->lock);
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if (WARN_ON_ONCE(!irq->refcount))
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@ -178,7 +170,7 @@ static int irq_get(struct mlx5_irq *irq)
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int err;
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mutex_lock(&irq->pool->lock);
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err = irq_get_locked(irq);
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err = mlx5_irq_get_locked(irq);
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mutex_unlock(&irq->pool->lock);
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return err;
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}
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@ -215,8 +207,8 @@ static bool irq_pool_is_sf_pool(struct mlx5_irq_pool *pool)
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return !strncmp("mlx5_sf", pool->name, strlen("mlx5_sf"));
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}
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static struct mlx5_irq *irq_request(struct mlx5_irq_pool *pool, int i,
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struct cpumask *affinity)
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struct mlx5_irq *mlx5_irq_alloc(struct mlx5_irq_pool *pool, int i,
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const struct cpumask *affinity)
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{
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struct mlx5_core_dev *dev = pool->dev;
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char name[MLX5_MAX_IRQ_NAME];
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@ -306,79 +298,6 @@ int mlx5_irq_get_index(struct mlx5_irq *irq)
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/* irq_pool API */
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/* creating an irq from irq_pool */
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static struct mlx5_irq *irq_pool_create_irq(struct mlx5_irq_pool *pool,
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struct cpumask *affinity)
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{
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u32 irq_index;
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int err;
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err = xa_alloc(&pool->irqs, &irq_index, NULL, pool->xa_num_irqs,
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GFP_KERNEL);
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if (err)
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return ERR_PTR(err);
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return irq_request(pool, irq_index, affinity);
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}
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/* looking for the irq with the smallest refcount and the same affinity */
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static struct mlx5_irq *irq_pool_find_least_loaded(struct mlx5_irq_pool *pool,
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struct cpumask *affinity)
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{
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int start = pool->xa_num_irqs.min;
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int end = pool->xa_num_irqs.max;
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struct mlx5_irq *irq = NULL;
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struct mlx5_irq *iter;
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unsigned long index;
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lockdep_assert_held(&pool->lock);
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xa_for_each_range(&pool->irqs, index, iter, start, end) {
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if (!cpumask_equal(iter->mask, affinity))
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continue;
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if (iter->refcount < pool->min_threshold)
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return iter;
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if (!irq || iter->refcount < irq->refcount)
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irq = iter;
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}
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return irq;
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}
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/* requesting an irq from a given pool according to given affinity */
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static struct mlx5_irq *irq_pool_request_affinity(struct mlx5_irq_pool *pool,
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struct cpumask *affinity)
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{
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struct mlx5_irq *least_loaded_irq, *new_irq;
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mutex_lock(&pool->lock);
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least_loaded_irq = irq_pool_find_least_loaded(pool, affinity);
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if (least_loaded_irq &&
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least_loaded_irq->refcount < pool->min_threshold)
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goto out;
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new_irq = irq_pool_create_irq(pool, affinity);
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if (IS_ERR(new_irq)) {
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if (!least_loaded_irq) {
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mlx5_core_err(pool->dev, "Didn't find a matching IRQ. err = %ld\n",
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PTR_ERR(new_irq));
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mutex_unlock(&pool->lock);
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return new_irq;
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}
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/* We failed to create a new IRQ for the requested affinity,
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* sharing existing IRQ.
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*/
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goto out;
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}
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least_loaded_irq = new_irq;
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goto unlock;
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out:
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irq_get_locked(least_loaded_irq);
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if (least_loaded_irq->refcount > pool->max_threshold)
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mlx5_core_dbg(pool->dev, "IRQ %u overloaded, pool_name: %s, %u EQs on this irq\n",
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least_loaded_irq->irqn, pool->name,
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least_loaded_irq->refcount / MLX5_EQ_REFS_PER_IRQ);
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unlock:
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mutex_unlock(&pool->lock);
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return least_loaded_irq;
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}
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/* requesting an irq from a given pool according to given index */
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static struct mlx5_irq *
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irq_pool_request_vector(struct mlx5_irq_pool *pool, int vecidx,
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@ -389,10 +308,10 @@ irq_pool_request_vector(struct mlx5_irq_pool *pool, int vecidx,
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mutex_lock(&pool->lock);
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irq = xa_load(&pool->irqs, vecidx);
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if (irq) {
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irq_get_locked(irq);
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mlx5_irq_get_locked(irq);
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goto unlock;
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}
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irq = irq_request(pool, vecidx, affinity);
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irq = mlx5_irq_alloc(pool, vecidx, affinity);
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unlock:
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mutex_unlock(&pool->lock);
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return irq;
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@ -457,7 +376,7 @@ struct mlx5_irq *mlx5_ctrl_irq_request(struct mlx5_core_dev *dev)
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/* Allocate the IRQ in the last index of the pool */
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irq = irq_pool_request_vector(pool, pool->xa_num_irqs.max, req_mask);
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} else {
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irq = irq_pool_request_affinity(pool, req_mask);
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irq = mlx5_irq_affinity_request(pool, req_mask);
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}
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free_cpumask_var(req_mask);
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@ -489,7 +408,7 @@ struct mlx5_irq *mlx5_irq_request(struct mlx5_core_dev *dev, u16 vecidx,
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/* In case an SF user request IRQ with vecidx */
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irq = irq_pool_request_vector(pool, vecidx, NULL);
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else
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irq = irq_pool_request_affinity(pool, affinity);
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irq = mlx5_irq_affinity_request(pool, affinity);
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goto out;
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}
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pf_irq:
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31
drivers/net/ethernet/mellanox/mlx5/core/pci_irq.h
Normal file
31
drivers/net/ethernet/mellanox/mlx5/core/pci_irq.h
Normal file
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@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#ifndef __PCI_IRQ_H__
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#define __PCI_IRQ_H__
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#include <linux/mlx5/driver.h>
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#define MLX5_MAX_IRQ_NAME (32)
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/* max irq_index is 2047, so four chars */
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#define MLX5_MAX_IRQ_IDX_CHARS (4)
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#define MLX5_EQ_REFS_PER_IRQ (2)
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struct mlx5_irq;
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struct mlx5_irq_pool {
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char name[MLX5_MAX_IRQ_NAME - MLX5_MAX_IRQ_IDX_CHARS];
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struct xa_limit xa_num_irqs;
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struct mutex lock; /* sync IRQs creations */
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struct xarray irqs;
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u32 max_threshold;
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u32 min_threshold;
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struct mlx5_core_dev *dev;
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};
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struct mlx5_irq *mlx5_irq_alloc(struct mlx5_irq_pool *pool, int i,
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const struct cpumask *affinity);
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int mlx5_irq_get_locked(struct mlx5_irq *irq);
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int mlx5_irq_read_locked(struct mlx5_irq *irq);
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#endif /* __PCI_IRQ_H__ */
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