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arm64: dts: qcom: sc7280: fix display port phy reg property

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Existing display port phy reg property is derived from usb phy which
map display port phy pcs to wrong address which cause aux init
with wrong address and prevent both dpcd read and write from working.
Fix this problem by assigning correct pcs address to display port
phy reg property.

Fixes: bb9efa59c6 ("arm64: dts: qcom: sc7280: Add USB related nodes")
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631216998-10049-1-git-send-email-khsieh@codeaurora.org
This commit is contained in:
Kuogee Hsieh 2021-09-09 12:49:58 -07:00 committed by Bjorn Andersson
parent be0416a3f9
commit 425f30cc84
1 changed files with 2 additions and 6 deletions
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8
arch/arm64/boot/dts/qcom/sc7280.dtsi
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@ -1258,15 +1258,11 @@ usb_1_ssphy: usb3-phy@88e9200 {
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eac00 0 0x400>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>,
<0 0x088eaa00 0 0x100>;
<0 0x088ea800 0 0x200>;
#phy-cells = <0>;
#clock-cells = <1>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
};