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watchdog: qcom: Remove incorrect usage of QCOM_WDT_ENABLE_IRQ
commita4f3407c41
upstream. As per register documentation, QCOM_WDT_ENABLE_IRQ which is BIT(1) of watchdog control register is wakeup interrupt enable bit and not related to bark interrupt at all, BIT(0) is used for that. So remove incorrect usage of this bit when supporting bark irq for pre-timeout notification. Currently with this bit set and bark interrupt specified, pre-timeout notification and/or watchdog reset/bite does not occur. Fixes:36375491a4
("watchdog: qcom: support pre-timeout when the bark irq is available") Cc: stable@vger.kernel.org Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210126150241.10009-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 1 additions and 12 deletions
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@ -22,7 +22,6 @@ enum wdt_reg {
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};
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#define QCOM_WDT_ENABLE BIT(0)
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#define QCOM_WDT_ENABLE_IRQ BIT(1)
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static const u32 reg_offset_data_apcs_tmr[] = {
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[WDT_RST] = 0x38,
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@ -58,16 +57,6 @@ struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
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return container_of(wdd, struct qcom_wdt, wdd);
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}
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static inline int qcom_get_enable(struct watchdog_device *wdd)
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{
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int enable = QCOM_WDT_ENABLE;
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if (wdd->pretimeout)
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enable |= QCOM_WDT_ENABLE_IRQ;
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return enable;
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}
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static irqreturn_t qcom_wdt_isr(int irq, void *arg)
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{
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struct watchdog_device *wdd = arg;
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@ -86,7 +75,7 @@ static int qcom_wdt_start(struct watchdog_device *wdd)
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writel(1, wdt_addr(wdt, WDT_RST));
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writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
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writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
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writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN));
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writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
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return 0;
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}
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