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arm64: dts: Amlogic updates for v5.7 (round 2)
- G12[ab]: add SPI support, enable on odroid-n2 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl55M5UACgkQWTcYmtP7 xmX7mQ/+Pc4Px4VT81SkuLMAGoXJQnV0u+C1w3pWJYB3Od64QYE8woM8dVcacG/R DJWBpIUdQGad7J3ZygWZTwt2dW1+HggA+/t1Q4FzNv8hWOXzRH+WJB/Wa0zoGxA9 q8EM39zhmaSh7LFaakelq+pHpD+GIbNShfGibv5vGs6SgxaZ4SC58jHH5kwYQiqC 6pKs3P3CviCdj+s3OyTEsMGIPyuPFlC+iLFZdX7Pgaarsw/XXsOYQdodvQYzy8gL VEmQ4Sls2LN5Xuczx9PLXQuUOgcnL/4JvwW2vkqKS7c5HSiJ0TfwA5DUUZpHPOsC BSvflUGqltejRt8V0+KkRXtmsILJE5GBqk9pTN9RUpEf3POqoGfriK11hcHsa93X 1PtoxYCVrDJBChQYCIIJ2Va1Ktv5A06Ew+u1cDcEMIte2iSFL9T4DOe7Uaj1/7ne ZxKRDs4u3QsIrK6ULzonVznlS6hGlshM0zfdzOFIZcmvj0dl3w4jFljXo+1Jd71y gagjRZrc/M1J4vNTqIzRHrqBPsTEokvzTU/R3tWCBU5INmBtcAxQLDMh4PNqs/Ti 2t8BUMdND6wUclkE3GL9ZBYKuAx/jWrIZUvl68R3r6OoqokL7hvrbUcyZr92IDry rTZcpQWwHbFbFHEVwlG1h/yKdRTw1I0+WKRdsXGemsYog2lIApQ= =feMw -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.7 (round 2) - G12[ab]: add SPI support, enable on odroid-n2 * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node arm64: dts: khadas-vim3: add SPIFC controller node arm64: dts: meson-g12: add the SPIFC nodes arm64: dts: meson-g12: split emmc pins to select 4 or 8 bus width arm64: dts: meson-g12-common: add spicc controller nodes dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs dt-bindings: clk: meson: add the gxl internal dac gate Link: https://lore.kernel.org/r/7hftdyhfq4.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
4287ec9afa
11 changed files with 177 additions and 17 deletions
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@ -295,17 +295,9 @@ mux {
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};
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};
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emmc_pins: emmc {
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emmc_ctrl_pins: emmc-ctrl {
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mux-0 {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7",
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"emmc_cmd";
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groups = "emmc_cmd";
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function = "emmc";
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bias-pull-up;
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drive-strength-microamp = <4000>;
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@ -319,6 +311,34 @@ mux-1 {
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};
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};
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emmc_data_4b_pins: emmc-data-4b {
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mux-0 {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3";
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function = "emmc";
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bias-pull-up;
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drive-strength-microamp = <4000>;
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};
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};
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emmc_data_8b_pins: emmc-data-8b {
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mux-0 {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7";
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function = "emmc";
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bias-pull-up;
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drive-strength-microamp = <4000>;
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};
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};
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emmc_ds_pins: emmc-ds {
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mux {
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groups = "emmc_nand_ds";
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@ -573,6 +593,17 @@ mux {
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};
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};
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nor_pins: nor {
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mux {
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groups = "nor_d",
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"nor_q",
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"nor_c",
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"nor_cs";
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function = "nor";
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bias-disable;
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};
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};
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pdm_din0_a_pins: pdm-din0-a {
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mux {
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groups = "pdm_din0_a";
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@ -957,6 +988,57 @@ mux {
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};
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};
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spicc0_x_pins: spicc0-x {
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mux {
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groups = "spi0_mosi_x",
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"spi0_miso_x",
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"spi0_clk_x";
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function = "spi0";
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drive-strength-microamp = <4000>;
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bias-disable;
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};
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};
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spicc0_ss0_x_pins: spicc0-ss0-x {
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mux {
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groups = "spi0_ss0_x";
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function = "spi0";
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drive-strength-microamp = <4000>;
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bias-disable;
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};
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};
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spicc0_c_pins: spicc0-c {
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mux {
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groups = "spi0_mosi_c",
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"spi0_miso_c",
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"spi0_ss0_c",
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"spi0_clk_c";
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function = "spi0";
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drive-strength-microamp = <4000>;
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bias-disable;
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};
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};
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spicc1_pins: spicc1 {
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mux {
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groups = "spi1_mosi",
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"spi1_miso",
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"spi1_clk";
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function = "spi1";
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drive-strength-microamp = <4000>;
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};
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};
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spicc1_ss0_pins: spicc1-ss0 {
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mux {
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groups = "spi1_ss0";
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function = "spi1";
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drive-strength-microamp = <4000>;
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bias-disable;
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};
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};
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tdm_a_din0_pins: tdm-a-din0 {
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mux {
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groups = "tdm_a_din0";
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@ -2051,6 +2133,39 @@ gpio_intc: interrupt-controller@f080 {
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amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
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};
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spicc0: spi@13000 {
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compatible = "amlogic,meson-g12a-spicc";
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reg = <0x0 0x13000 0x0 0x44>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_SPICC0>,
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<&clkc CLKID_SPICC0_SCLK>;
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clock-names = "core", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spicc1: spi@15000 {
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compatible = "amlogic,meson-g12a-spicc";
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reg = <0x0 0x15000 0x0 0x44>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_SPICC1>,
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<&clkc CLKID_SPICC1_SCLK>;
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clock-names = "core", "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spifc: spi@14000 {
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compatible = "amlogic,meson-gxbb-spifc";
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status = "disabled";
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reg = <0x0 0x14000 0x0 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkc CLKID_CLK81>;
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};
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pwm_ef: pwm@19000 {
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compatible = "amlogic,meson-g12a-ee-pwm";
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reg = <0x0 0x19000 0x0 0x20>;
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@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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@ -472,7 +472,7 @@ &sd_emmc_b {
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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@ -271,7 +271,7 @@ &sd_emmc_b {
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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@ -443,7 +443,7 @@ &sd_emmc_b {
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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@ -435,7 +435,7 @@ &sd_emmc_b {
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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@ -451,6 +451,27 @@ &sd_emmc_c {
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vqmmc-supply = <&flash_1v8>;
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};
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/*
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* EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
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* and eMMC Data 4 to 7 pins.
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* Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
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* and change bus-width to 4 then spifc can be enabled.
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* The SW1 slide should also be set to the correct position.
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*/
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&spifc {
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status = "disabled";
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pinctrl-0 = <&nor_pins>;
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pinctrl-names = "default";
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mx25u64: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <104000000>;
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};
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};
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&tdmif_b {
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status = "okay";
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};
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@ -485,7 +485,7 @@ &sd_emmc_b {
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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@ -310,7 +310,7 @@ &sd_emmc_b {
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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@ -326,6 +326,26 @@ &sd_emmc_c {
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vqmmc-supply = <&emmc_1v8>;
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};
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/*
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* EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
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* and eMMC Data 4 to 7 pins.
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* Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
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* and change bus-width to 4 then spifc can be enabled.
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*/
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&spifc {
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status = "disabled";
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pinctrl-0 = <&nor_pins>;
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pinctrl-names = "default";
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w25q32: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "winbond,w25q128fw", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <104000000>;
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};
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};
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&uart_A {
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status = "okay";
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pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
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@ -518,7 +518,7 @@ &sd_emmc_b {
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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@ -143,5 +143,7 @@
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#define CLKID_CPU1_CLK 253
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#define CLKID_CPU2_CLK 254
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#define CLKID_CPU3_CLK 255
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#define CLKID_SPICC0_SCLK 258
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#define CLKID_SPICC1_SCLK 261
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#endif /* __G12A_CLKC_H */
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@ -146,5 +146,6 @@
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#define CLKID_CTS_VDAC 201
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#define CLKID_HDMI_TX 202
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#define CLKID_HDMI 205
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#define CLKID_ACODEC 206
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#endif /* __GXBB_CLKC_H */
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