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ARM: sun7i: Enable the I2C controllers
The Allwinner A20 shares the same I2C controller than the one that could be found on earlier SoCs from Allwinner. There is only a few more of these controllers. Add all of them in the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -329,6 +329,51 @@ uart7: serial@01c29c00 {
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status = "disabled";
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};
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i2c0: i2c@01c2ac00 {
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <0 7 1>;
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clocks = <&apb1_gates 0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@01c2b000 {
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <0 8 1>;
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clocks = <&apb1_gates 1>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c2: i2c@01c2b400 {
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <0 9 1>;
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clocks = <&apb1_gates 2>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c3: i2c@01c2b800 {
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2b800 0x400>;
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interrupts = <0 88 1>;
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clocks = <&apb1_gates 3>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c4: i2c@01c2bc00 {
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compatible = "allwinner,sun4i-i2c";
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reg = <0x01c2bc00 0x400>;
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interrupts = <0 89 1>;
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clocks = <&apb1_gates 15>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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