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powerpc/32s: Make pte_update() non atomic on 603 core
On 603 core, TLB miss handler don't do any change to the page tables so pte_update() doesn't need to be atomic. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/cc89d3c11fc9c742d0df3454a657a3a00be24046.1643538554.git.christophe.leroy@csgroup.eu
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1 changed files with 22 additions and 15 deletions
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@ -298,28 +298,35 @@ static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, p
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unsigned long clr, unsigned long set, int huge)
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{
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pte_basic_t old;
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unsigned long tmp;
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__asm__ __volatile__(
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if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
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unsigned long tmp;
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asm volatile(
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#ifndef CONFIG_PTE_64BIT
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"1: lwarx %0, 0, %3\n"
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" andc %1, %0, %4\n"
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"1: lwarx %0, 0, %3\n"
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" andc %1, %0, %4\n"
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#else
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"1: lwarx %L0, 0, %3\n"
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" lwz %0, -4(%3)\n"
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" andc %1, %L0, %4\n"
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"1: lwarx %L0, 0, %3\n"
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" lwz %0, -4(%3)\n"
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" andc %1, %L0, %4\n"
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#endif
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" or %1, %1, %5\n"
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" stwcx. %1, 0, %3\n"
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" bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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" or %1, %1, %5\n"
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" stwcx. %1, 0, %3\n"
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" bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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#ifndef CONFIG_PTE_64BIT
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: "r" (p),
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: "r" (p),
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#else
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: "b" ((unsigned long)(p) + 4),
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: "b" ((unsigned long)(p) + 4),
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#endif
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"r" (clr), "r" (set), "m" (*p)
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: "cc" );
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"r" (clr), "r" (set), "m" (*p)
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: "cc" );
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} else {
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old = pte_val(*p);
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*p = __pte((old & ~(pte_basic_t)clr) | set);
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}
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return old;
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}
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