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dt: amd-seattle: add description of the SATA/CCP SMMUs

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Add descriptions of the SMMUs that cover the SATA controller(s)
on the AMD Seattle SOC. The CCP crypto accelerator shares its
SMMU with the second SATA controller, which is only enabled on
B1 silicon.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Ard Biesheuvel 2019-12-03 15:23:04 +00:00 committed by Arnd Bergmann
parent dd5c160655
commit 429863e767
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GPG key ID: 9A6C79EFE60018D9
1 changed files with 26 additions and 0 deletions
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26
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
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@ -70,6 +70,7 @@ sata0: sata@e0300000 {
reg = <0 0xe0300000 0 0xf0000>;
interrupts = <0 355 4>;
clocks = <&sataclk_333mhz>;
iommus = <&sata0_smmu 0x0 0x1f>;
dma-coherent;
};
@ -80,6 +81,27 @@ sata1: sata@e0d00000 {
reg = <0 0xe0d00000 0 0xf0000>;
interrupts = <0 354 4>;
clocks = <&sataclk_333mhz>;
iommus = <&sata1_smmu 0x0e>,
<&sata1_smmu 0x0f>,
<&sata1_smmu 0x1e>;
dma-coherent;
};
sata0_smmu: iommu@e0200000 {
compatible = "arm,mmu-401";
reg = <0 0xe0200000 0 0x10000>;
#global-interrupts = <1>;
interrupts = <0 332 4>, <0 332 4>;
#iommu-cells = <2>;
dma-coherent;
};
sata1_smmu: iommu@e0c00000 {
compatible = "arm,mmu-401";
reg = <0 0xe0c00000 0 0x10000>;
#global-interrupts = <1>;
interrupts = <0 331 4>, <0 331 4>;
#iommu-cells = <1>;
dma-coherent;
};
@ -201,6 +223,10 @@ ccp0: ccp@e0100000 {
reg = <0 0xe0100000 0 0x10000>;
interrupts = <0 3 4>;
dma-coherent;
iommus = <&sata1_smmu 0x00>,
<&sata1_smmu 0x02>,
<&sata1_smmu 0x40>,
<&sata1_smmu 0x42>;
};
pcie0: pcie@f0000000 {