mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 13:53:33 +00:00
serial: 8250_bcm7271: improve bcm7271 8250 port
The 8250 BCM7271 UART is not a direct match to PORT_16550A and other generic ports do not match its hardware capabilities. PORT_ALTR matches the rx trigger levels, but its vendor configurations are not compatible. Unfortunately this means we need to create another port to fully capture the hardware capabilities of the BCM7271 UART. To alleviate some latency pressures, we default the rx trigger level to 8. Signed-off-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Doug Berger <opendmb@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/1692643978-16570-1-git-send-email-justin.chen@broadcom.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
b4a778303e
commit
42a569cd0d
3 changed files with 12 additions and 3 deletions
|
@ -1042,7 +1042,7 @@ static int brcmuart_probe(struct platform_device *pdev)
|
|||
dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not ");
|
||||
|
||||
memset(&up, 0, sizeof(up));
|
||||
up.port.type = PORT_16550A;
|
||||
up.port.type = PORT_BCM7271;
|
||||
up.port.uartclk = clk_rate;
|
||||
up.port.dev = dev;
|
||||
up.port.mapbase = mapbase;
|
||||
|
@ -1056,8 +1056,6 @@ static int brcmuart_probe(struct platform_device *pdev)
|
|||
| UPF_FIXED_PORT | UPF_FIXED_TYPE;
|
||||
up.port.dev = dev;
|
||||
up.port.private_data = priv;
|
||||
up.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
|
||||
up.port.fifosize = 32;
|
||||
|
||||
/* Check for a fixed line number */
|
||||
ret = of_alias_get_id(np, "serial");
|
||||
|
|
|
@ -322,6 +322,14 @@ static const struct serial8250_config uart_config[] = {
|
|||
.rxtrig_bytes = {2, 66, 130, 194},
|
||||
.flags = UART_CAP_FIFO,
|
||||
},
|
||||
[PORT_BCM7271] = {
|
||||
.name = "Broadcom BCM7271 UART",
|
||||
.fifo_size = 32,
|
||||
.tx_loadsz = 32,
|
||||
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
|
||||
.rxtrig_bytes = {1, 8, 16, 30},
|
||||
.flags = UART_CAP_FIFO | UART_CAP_AFE,
|
||||
},
|
||||
};
|
||||
|
||||
/* Uart divisor latch read */
|
||||
|
|
|
@ -123,6 +123,9 @@
|
|||
/* Xilinx uartlite */
|
||||
#define PORT_UARTLITE 74
|
||||
|
||||
/* Broadcom BCM7271 UART */
|
||||
#define PORT_BCM7271 76
|
||||
|
||||
/* Broadcom SB1250, etc. SOC */
|
||||
#define PORT_SB1250_DUART 77
|
||||
|
||||
|
|
Loading…
Reference in a new issue