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drm/amd/powerplay: Fix enum mismatch
In several locations the driver uses AMD_CG_STATE_UNGATE (type enum amd_clockgating_state) instead of AMD_PG_STATE_UNGATE (type enum amd_powergating_stat) and vice versa. Both constants have the same value, so this doesn't cause any problems, but we still want to pass the correct type. Fixing the mismatch resolves multiple warnings like this when building with clang: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:169:7: error: implicit conversion from enumeration type 'enum amd_powergating_state' to different enumeration type 'enum amd_clockgating_state' [-Werror,-Wenum-conversion] AMD_PG_STATE_UNGATE); Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7e452ce9c9
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2 changed files with 5 additions and 5 deletions
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@ -166,10 +166,10 @@ void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
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cz_dpm_powerup_uvd(hwmgr);
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cz_dpm_powerup_uvd(hwmgr);
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cgs_set_clockgating_state(hwmgr->device,
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_UNGATE);
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AMD_CG_STATE_UNGATE);
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cgs_set_powergating_state(hwmgr->device,
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_UNGATE);
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AMD_PG_STATE_UNGATE);
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cz_dpm_update_uvd_dpm(hwmgr, false);
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cz_dpm_update_uvd_dpm(hwmgr, false);
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}
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}
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@ -197,11 +197,11 @@ void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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cgs_set_clockgating_state(
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cgs_set_clockgating_state(
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hwmgr->device,
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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AMD_CG_STATE_UNGATE);
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cgs_set_powergating_state(
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cgs_set_powergating_state(
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hwmgr->device,
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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AMD_PG_STATE_UNGATE);
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cz_dpm_update_vce_dpm(hwmgr);
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cz_dpm_update_vce_dpm(hwmgr);
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cz_enable_disable_vce_dpm(hwmgr, true);
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cz_enable_disable_vce_dpm(hwmgr, true);
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}
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}
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@ -162,7 +162,7 @@ void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
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AMD_CG_STATE_UNGATE);
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AMD_CG_STATE_UNGATE);
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cgs_set_powergating_state(hwmgr->device,
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_UNGATE);
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AMD_PG_STATE_UNGATE);
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smu7_update_uvd_dpm(hwmgr, false);
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smu7_update_uvd_dpm(hwmgr, false);
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}
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}
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