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imx-drm vblank IRQ control, fence support, and of endpoint helpers

Browse source 
- Add and make use of drm_of_active_endpoint helpers
 - Silence a noisy dev_info into a dev_dbg
 - Stop touching primary fb on pageflips
 - Track flip state explicitly
 - Keep GEM buffer objects referenced while scanout is active
 - Implement fence sync by deferring flips to a workqueue for
   dma-bufs with pending fences
 - Actually disable vblank IRQs while they are not needed
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Merge tag 'imx-drm-next-20160301' of git://git.pengutronix.de/git/pza/linux into drm-next

imx-drm vblank IRQ control, fence support, and of endpoint helpers

- Add and make use of drm_of_active_endpoint helpers
- Silence a noisy dev_info into a dev_dbg
- Stop touching primary fb on pageflips
- Track flip state explicitly
- Keep GEM buffer objects referenced while scanout is active
- Implement fence sync by deferring flips to a workqueue for
  dma-bufs with pending fences
- Actually disable vblank IRQs while they are not needed

* tag 'imx-drm-next-20160301' of git://git.pengutronix.de/git/pza/linux:
  drm/imx: only enable vblank IRQs when needed
  drm/imx: implement fence sync
  drm/imx: keep GEM object referenced as long as scanout is active
  drm/imx: track flip state explicitly
  drm/imx: don't touch primary fb on pageflip
  drm/imx: ipuv3 plane: Replace dev_info with dev_dbg if a plane's CRTC changes
  gpu: ipu-v3: ipu-dc: Simplify display controller microcode setup
  drm/rockchip: remove rockchip_drm_encoder_get_mux_id
  drm/imx: remove imx_drm_encoder_get_mux_id
  drm: add drm_of_encoder_active_endpoint helpers
This commit is contained in:
Dave Airlie 2016-03-02 17:52:51 +10:00
commit 42e8560678
13 changed files with 222 additions and 109 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

34
drivers/gpu/drm/drm_of.c
View file

@ -149,3 +149,37 @@ int drm_of_component_probe(struct device *dev,
return component_master_add_with_match(dev, m_ops, match);
}
EXPORT_SYMBOL(drm_of_component_probe);
/*
* drm_of_encoder_active_endpoint - return the active encoder endpoint
* @node: device tree node containing encoder input ports
* @encoder: drm_encoder
*
* Given an encoder device node and a drm_encoder with a connected crtc,
* parse the encoder endpoint connecting to the crtc port.
*/
int drm_of_encoder_active_endpoint(struct device_node *node,
struct drm_encoder *encoder,
struct of_endpoint *endpoint)
{
struct device_node *ep;
struct drm_crtc *crtc = encoder->crtc;
struct device_node *port;
int ret;
if (!node || !crtc)
return -EINVAL;
for_each_endpoint_of_node(node, ep) {
port = of_graph_get_remote_port(ep);
of_node_put(port);
if (port == crtc->port) {
ret = of_graph_parse_endpoint(ep, endpoint);
of_node_put(ep);
return ret;
}
}
return -EINVAL;
}
EXPORT_SYMBOL_GPL(drm_of_encoder_active_endpoint);

2
drivers/gpu/drm/imx/dw_hdmi-imx.c
View file

@ -118,7 +118,7 @@ static void dw_hdmi_imx_encoder_mode_set(struct drm_encoder *encoder,
static void dw_hdmi_imx_encoder_commit(struct drm_encoder *encoder)
{
struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
IMX6Q_GPR3_HDMI_MUX_CTL_MASK,

31
drivers/gpu/drm/imx/imx-drm-core.c
View file

@ -17,7 +17,6 @@
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_fb_helper.h>
@ -412,36 +411,6 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
}
EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
/*
* @node: device tree node containing encoder input ports
* @encoder: drm_encoder
*/
int imx_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder)
{
struct imx_drm_crtc *imx_crtc = imx_drm_find_crtc(encoder->crtc);
struct device_node *ep;
struct of_endpoint endpoint;
struct device_node *port;
int ret;
if (!node || !imx_crtc)
return -EINVAL;
for_each_endpoint_of_node(node, ep) {
port = of_graph_get_remote_port(ep);
of_node_put(port);
if (port == imx_crtc->crtc->port) {
ret = of_graph_parse_endpoint(ep, &endpoint);
of_node_put(ep);
return ret ? ret : endpoint.port;
}
}
return -EINVAL;
}
EXPORT_SYMBOL_GPL(imx_drm_encoder_get_mux_id);
static const struct drm_ioctl_desc imx_drm_ioctls[] = {
/* none so far */
};

2
drivers/gpu/drm/imx/imx-drm.h
View file

@ -46,8 +46,6 @@ int imx_drm_set_bus_format_pins(struct drm_encoder *encoder,
int imx_drm_set_bus_format(struct drm_encoder *encoder,
u32 bus_format);
int imx_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder);
int imx_drm_encoder_parse_of(struct drm_device *drm,
struct drm_encoder *encoder, struct device_node *np);

5
drivers/gpu/drm/imx/imx-ldb.c
View file

@ -19,6 +19,7 @@
#include <drm/drmP.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
@ -208,7 +209,7 @@ static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
struct imx_ldb *ldb = imx_ldb_ch->ldb;
int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
drm_panel_prepare(imx_ldb_ch->panel);
@ -258,7 +259,7 @@ static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
unsigned long serial_clk;
unsigned long di_clk = mode->clock * 1000;
int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
if (mode->clock > 170000) {
dev_warn(ldb->dev,

133
drivers/gpu/drm/imx/ipuv3-crtc.c
View file

@ -22,6 +22,8 @@
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/reservation.h>
#include <linux/dma-buf.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>
@ -31,6 +33,23 @@
#define DRIVER_DESC "i.MX IPUv3 Graphics"
enum ipu_flip_status {
IPU_FLIP_NONE,
IPU_FLIP_PENDING,
IPU_FLIP_SUBMITTED,
};
struct ipu_flip_work {
struct work_struct unref_work;
struct drm_gem_object *bo;
struct drm_pending_vblank_event *page_flip_event;
struct work_struct fence_work;
struct ipu_crtc *crtc;
struct fence *excl;
unsigned shared_count;
struct fence **shared;
};
struct ipu_crtc {
struct device *dev;
struct drm_crtc base;
@ -42,8 +61,9 @@ struct ipu_crtc {
struct ipu_dc *dc;
struct ipu_di *di;
int enabled;
struct drm_pending_vblank_event *page_flip_event;
struct drm_framebuffer *newfb;
enum ipu_flip_status flip_state;
struct workqueue_struct *flip_queue;
struct ipu_flip_work *flip_work;
int irq;
u32 bus_format;
int di_hsync_pin;
@ -102,15 +122,45 @@ static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
}
}
static void ipu_flip_unref_work_func(struct work_struct *__work)
{
struct ipu_flip_work *work =
container_of(__work, struct ipu_flip_work, unref_work);
drm_gem_object_unreference_unlocked(work->bo);
kfree(work);
}
static void ipu_flip_fence_work_func(struct work_struct *__work)
{
struct ipu_flip_work *work =
container_of(__work, struct ipu_flip_work, fence_work);
int i;
/* wait for all fences attached to the FB obj to signal */
if (work->excl) {
fence_wait(work->excl, false);
fence_put(work->excl);
}
for (i = 0; i < work->shared_count; i++) {
fence_wait(work->shared[i], false);
fence_put(work->shared[i]);
}
work->crtc->flip_state = IPU_FLIP_SUBMITTED;
}
static int ipu_page_flip(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_pending_vblank_event *event,
uint32_t page_flip_flags)
{
struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
struct ipu_flip_work *flip_work;
int ret;
if (ipu_crtc->newfb)
if (ipu_crtc->flip_state != IPU_FLIP_NONE)
return -EBUSY;
ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
@ -121,11 +171,58 @@ static int ipu_page_flip(struct drm_crtc *crtc,
return ret;
}
ipu_crtc->newfb = fb;
ipu_crtc->page_flip_event = event;
crtc->primary->fb = fb;
flip_work = kzalloc(sizeof *flip_work, GFP_KERNEL);
if (!flip_work) {
ret = -ENOMEM;
goto put_vblank;
}
INIT_WORK(&flip_work->unref_work, ipu_flip_unref_work_func);
flip_work->page_flip_event = event;
/* get BO backing the old framebuffer and take a reference */
flip_work->bo = &drm_fb_cma_get_gem_obj(crtc->primary->fb, 0)->base;
drm_gem_object_reference(flip_work->bo);
ipu_crtc->flip_work = flip_work;
/*
* If the object has a DMABUF attached, we need to wait on its fences
* if there are any.
*/
if (cma_obj->base.dma_buf) {
INIT_WORK(&flip_work->fence_work, ipu_flip_fence_work_func);
flip_work->crtc = ipu_crtc;
ret = reservation_object_get_fences_rcu(
cma_obj->base.dma_buf->resv, &flip_work->excl,
&flip_work->shared_count, &flip_work->shared);
if (unlikely(ret)) {
DRM_ERROR("failed to get fences for buffer\n");
goto free_flip_work;
}
/* No need to queue the worker if the are no fences */
if (!flip_work->excl && !flip_work->shared_count) {
ipu_crtc->flip_state = IPU_FLIP_SUBMITTED;
} else {
ipu_crtc->flip_state = IPU_FLIP_PENDING;
queue_work(ipu_crtc->flip_queue,
&flip_work->fence_work);
}
} else {
ipu_crtc->flip_state = IPU_FLIP_SUBMITTED;
}
return 0;
free_flip_work:
drm_gem_object_unreference_unlocked(flip_work->bo);
kfree(flip_work);
ipu_crtc->flip_work = NULL;
put_vblank:
imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
return ret;
}
static const struct drm_crtc_funcs ipu_crtc_funcs = {
@ -209,12 +306,12 @@ static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
{
unsigned long flags;
struct drm_device *drm = ipu_crtc->base.dev;
struct ipu_flip_work *work = ipu_crtc->flip_work;
spin_lock_irqsave(&drm->event_lock, flags);
if (ipu_crtc->page_flip_event)
if (work->page_flip_event)
drm_crtc_send_vblank_event(&ipu_crtc->base,
ipu_crtc->page_flip_event);
ipu_crtc->page_flip_event = NULL;
work->page_flip_event);
imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
spin_unlock_irqrestore(&drm->event_lock, flags);
}
@ -225,13 +322,15 @@ static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
imx_drm_handle_vblank(ipu_crtc->imx_crtc);
if (ipu_crtc->newfb) {
if (ipu_crtc->flip_state == IPU_FLIP_SUBMITTED) {
struct ipu_plane *plane = ipu_crtc->plane[0];
ipu_crtc->newfb = NULL;
ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
plane->x, plane->y);
ipu_crtc_handle_pageflip(ipu_crtc);
queue_work(ipu_crtc->flip_queue,
&ipu_crtc->flip_work->unref_work);
ipu_crtc->flip_state = IPU_FLIP_NONE;
}
return IRQ_HANDLED;
@ -280,11 +379,18 @@ static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
static int ipu_enable_vblank(struct drm_crtc *crtc)
{
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
enable_irq(ipu_crtc->irq);
return 0;
}
static void ipu_disable_vblank(struct drm_crtc *crtc)
{
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
disable_irq_nosync(ipu_crtc->irq);
}
static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
@ -395,6 +501,10 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
goto err_put_plane_res;
}
/* Only enable IRQ when we actually need it to trigger work. */
disable_irq(ipu_crtc->irq);
ipu_crtc->flip_queue = create_singlethread_workqueue("ipu-crtc-flip");
return 0;
@ -437,6 +547,7 @@ static void ipu_drm_unbind(struct device *dev, struct device *master,
imx_drm_remove_crtc(ipu_crtc->imx_crtc);
destroy_workqueue(ipu_crtc->flip_queue);
ipu_plane_put_resources(ipu_crtc->plane[0]);
ipu_put_resources(ipu_crtc);
}

2
drivers/gpu/drm/imx/ipuv3-plane.c
View file

@ -338,7 +338,7 @@ static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
}
if (crtc != plane->crtc)
dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
plane->crtc, crtc);
plane->crtc = crtc;

2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
View file

@ -878,7 +878,7 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
int mux = rockchip_drm_encoder_get_mux_id(dsi->dev->of_node, encoder);
int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
u32 interface_pix_fmt;
u32 val;

2
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
View file

@ -204,7 +204,7 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
ROCKCHIP_OUT_MODE_AAAA);
mux = rockchip_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
if (mux)
val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16);
else

30
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View file

@ -384,36 +384,6 @@ static const struct dev_pm_ops rockchip_drm_pm_ops = {
rockchip_drm_sys_resume)
};
/*
* @node: device tree node containing encoder input ports
* @encoder: drm_encoder
*/
int rockchip_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder)
{
struct device_node *ep;
struct drm_crtc *crtc = encoder->crtc;
struct of_endpoint endpoint;
struct device_node *port;
int ret;
if (!node || !crtc)
return -EINVAL;
for_each_endpoint_of_node(node, ep) {
port = of_graph_get_remote_port(ep);
of_node_put(port);
if (port == crtc->port) {
ret = of_graph_parse_endpoint(ep, &endpoint);
of_node_put(ep);
return ret ?: endpoint.id;
}
}
return -EINVAL;
}
EXPORT_SYMBOL_GPL(rockchip_drm_encoder_get_mux_id);
static int compare_of(struct device *dev, void *data)
{
struct device_node *np = data;

2
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View file

@ -67,8 +67,6 @@ void rockchip_drm_atomic_work(struct work_struct *work);
int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
const struct rockchip_crtc_funcs *crtc_funcs);
void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc);
int rockchip_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder);
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
int out_mode);
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,

53
drivers/gpu/ipu-v3/ipu-dc.c
View file

@ -171,6 +171,7 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
u32 bus_format, u32 width)
{
struct ipu_dc_priv *priv = dc->priv;
int addr, sync;
u32 reg = 0;
int map;
@ -182,41 +183,39 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
return map;
}
/*
* In interlaced mode we need more counters to create the asymmetric
* per-field VSYNC signals. The pixel active signal synchronising DC
* to DI moves to signal generator #6 (see ipu-di.c). In progressive
* mode counter #5 is used.
*/
sync = interlaced ? 6 : 5;
/* Reserve 5 microcode template words for each DI */
if (dc->di)
addr = 5;
else
addr = 0;
if (interlaced) {
int addr;
if (dc->di)
addr = 1;
else
addr = 0;
dc_link_event(dc, DC_EVT_NL, addr, 3);
dc_link_event(dc, DC_EVT_EOL, addr, 2);
dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
/* Init template microcode */
dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, 6, 1);
dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
} else {
if (dc->di) {
dc_link_event(dc, DC_EVT_NL, 2, 3);
dc_link_event(dc, DC_EVT_EOL, 3, 2);
dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
/* Init template microcode */
dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
} else {
dc_link_event(dc, DC_EVT_NL, 5, 3);
dc_link_event(dc, DC_EVT_EOL, 6, 2);
dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
/* Init template microcode */
dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
}
dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
/* Init template microcode */
dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
}
dc_link_event(dc, DC_EVT_NF, 0, 0);
dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
dc_link_event(dc, DC_EVT_EOF, 0, 0);

33
include/drm/drm_of.h
View file

@ -1,9 +1,12 @@
#ifndef __DRM_OF_H__
#define __DRM_OF_H__
#include <linux/of_graph.h>
struct component_master_ops;
struct device;
struct drm_device;
struct drm_encoder;
struct device_node;
#ifdef CONFIG_OF
@ -12,6 +15,9 @@ extern uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
extern int drm_of_component_probe(struct device *dev,
int (*compare_of)(struct device *, void *),
const struct component_master_ops *m_ops);
extern int drm_of_encoder_active_endpoint(struct device_node *node,
struct drm_encoder *encoder,
struct of_endpoint *endpoint);
#else
static inline uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
struct device_node *port)
@ -26,6 +32,33 @@ drm_of_component_probe(struct device *dev,
{
return -EINVAL;
}
static inline int drm_of_encoder_active_endpoint(struct device_node *node,
struct drm_encoder *encoder,
struct of_endpoint *endpoint)
{
return -EINVAL;
}
#endif
static inline int drm_of_encoder_active_endpoint_id(struct device_node *node,
struct drm_encoder *encoder)
{
struct of_endpoint endpoint;
int ret = drm_of_encoder_active_endpoint(node, encoder,
&endpoint);
return ret ?: endpoint.id;
}
static inline int drm_of_encoder_active_port_id(struct device_node *node,
struct drm_encoder *encoder)
{
struct of_endpoint endpoint;
int ret = drm_of_encoder_active_endpoint(node, encoder,
&endpoint);
return ret ?: endpoint.port;
}
#endif /* __DRM_OF_H__ */