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OMAP2+ clock: clean up clkt_clksel.c
This patch cleans up arch/arm/mach-omap2/clkt_clksel.c. It: - makes several functions static that are not called outside the file; - adds documentation; - makes some code paths easier to read (hopefully), by breaking up compound statements and removing redundant checks; - converts some pr_err()s that indicate clock tree data problems into WARN()s, so they are more likely to be noticed; - and moves omap2_clk_round_rate() back into mach-omap2/clock.c, its proper home, since it is not clksel-specific. Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
parent
d74b494971
commit
435699db6a
3 changed files with 301 additions and 212 deletions
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@ -12,8 +12,26 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX At some point these clksel clocks should be split into
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* "divider" clocks and "mux" clocks to better match the hardware.
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*
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* clksel clocks are clocks that do not have a fixed parent, or that
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* can divide their parent's rate, or possibly both at the same time, based
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* on the contents of a hardware register bitfield.
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*
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* All of the various mux and divider settings can be encoded into
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* struct clksel* data structures, and then these can be autogenerated
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* from some hardware database for each new chip generation. This
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* should avoid the need to write, review, and validate a lot of new
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* clock code for each new chip, since it can be exported from the SoC
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* design flow. This is now done on OMAP4.
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*
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* The fusion of mux and divider clocks is a software creation. In
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* hardware reality, the multiplexer (parent selection) and the
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* divider exist separately. XXX At some point these clksel clocks
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* should be split into "divider" clocks and "mux" clocks to better
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* match the hardware.
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*
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* (The name "clksel" comes from the name of the corresponding
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* register field in the OMAP2/3 family of SoCs.)
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*
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* XXX Currently these clocks are only used in the OMAP2/3/4 code, but
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* many of the OMAP1 clocks should be convertible to use this
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@ -29,14 +47,11 @@
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#include <plat/clock.h>
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#include "clock.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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/* Private functions */
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/**
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* _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
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* _get_clksel_by_parent() - return clksel struct for a given clk & parent
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* @clk: OMAP struct clk ptr to inspect
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* @src_clk: OMAP struct clk ptr of the parent clk to search for
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*
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@ -44,23 +59,19 @@
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* the element associated with the supplied parent clock address.
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* Returns a pointer to the struct clksel on success or NULL on error.
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*/
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static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
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struct clk *src_clk)
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static const struct clksel *_get_clksel_by_parent(struct clk *clk,
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struct clk *src_clk)
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{
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const struct clksel *clks;
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if (!clk->clksel)
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return NULL;
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for (clks = clk->clksel; clks->parent; clks++) {
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for (clks = clk->clksel; clks->parent; clks++)
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if (clks->parent == src_clk)
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break; /* Found the requested parent */
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}
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if (!clks->parent) {
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printk(KERN_ERR "clock: Could not find parent clock %s in "
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"clksel array of clock %s\n", src_clk->name,
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clk->name);
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/* This indicates a data problem */
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WARN(1, "clock: Could not find parent clock %s in clksel array "
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"of clock %s\n", src_clk->name, clk->name);
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return NULL;
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}
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@ -68,7 +79,7 @@ static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
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}
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/**
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* _omap2_clksel_get_src_field - find the new clksel divisor to use
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* _get_div_and_fieldval() - find the new clksel divisor and field value to use
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* @src_clk: planned new parent struct clk *
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* @clk: struct clk * that is being reparented
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* @field_val: pointer to a u32 to contain the register data for the divisor
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@ -82,14 +93,14 @@ static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
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* success (in this latter case, the corresponding register bitfield
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* value is passed back in the variable pointed to by @field_val)
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*/
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static u8 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
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u32 *field_val)
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static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
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u32 *field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr, *max_clkr;
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u8 max_div = 0;
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clks = _omap2_get_clksel_by_parent(clk, src_clk);
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clks = _get_clksel_by_parent(clk, src_clk);
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if (!clks)
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return 0;
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@ -113,9 +124,9 @@ static u8 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
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}
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if (max_div == 0) {
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WARN(1, "clock: Could not find divisor for "
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"clock %s parent %s\n", clk->name,
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src_clk->parent->name);
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/* This indicates an error in the clksel data */
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WARN(1, "clock: Could not find divisor for clock %s parent %s"
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"\n", clk->name, src_clk->parent->name);
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return 0;
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}
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@ -124,82 +135,141 @@ static u8 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
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return max_div;
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}
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/**
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* _write_clksel_reg() - program a clock's clksel register in hardware
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* @clk: struct clk * to program
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* @v: clksel bitfield value to program (with LSB at bit 0)
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*
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* Shift the clksel register bitfield value @v to its appropriate
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* location in the clksel register and write it in. This function
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* will ensure that the write to the clksel_reg reaches its
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* destination before returning -- important since PRM and CM register
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* accesses can be quite slow compared to ARM cycles -- but does not
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* take into account any time the hardware might take to switch the
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* clock source.
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*/
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static void _write_clksel_reg(struct clk *clk, u32 field_val)
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{
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u32 v;
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v = __raw_readl(clk->clksel_reg);
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v &= ~clk->clksel_mask;
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v |= field_val << __ffs(clk->clksel_mask);
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__raw_writel(v, clk->clksel_reg);
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v = __raw_readl(clk->clksel_reg); /* OCP barrier */
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}
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/**
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* _clksel_to_divisor() - turn clksel field value into integer divider
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* @clk: OMAP struct clk to use
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* @field_val: register field value to find
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*
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* Given a struct clk of a rate-selectable clksel clock, and a register field
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* value to search for, find the corresponding clock divisor. The register
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* field value should be pre-masked and shifted down so the LSB is at bit 0
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* before calling. Returns 0 on error or returns the actual integer divisor
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* upon success.
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*/
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static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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clks = _get_clksel_by_parent(clk, clk->parent);
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if (!clks)
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return 0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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if (clkr->val == field_val)
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break;
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}
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if (!clkr->div) {
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/* This indicates a data error */
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WARN(1, "clock: Could not find fieldval %d for clock %s parent "
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"%s\n", field_val, clk->name, clk->parent->name);
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return 0;
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}
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return clkr->div;
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}
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/**
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* _divisor_to_clksel() - turn clksel integer divisor into a field value
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* @clk: OMAP struct clk to use
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* @div: integer divisor to search for
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*
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* Given a struct clk of a rate-selectable clksel clock, and a clock
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* divisor, find the corresponding register field value. Returns the
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* register field value _before_ left-shifting (i.e., LSB is at bit
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* 0); or returns 0xFFFFFFFF (~0) upon error.
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*/
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static u32 _divisor_to_clksel(struct clk *clk, u32 div)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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/* should never happen */
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WARN_ON(div == 0);
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clks = _get_clksel_by_parent(clk, clk->parent);
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if (!clks)
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return ~0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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if (clkr->div == div)
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break;
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}
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if (!clkr->div) {
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pr_err("clock: Could not find divisor %d for clock %s parent "
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"%s\n", div, clk->name, clk->parent->name);
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return ~0;
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}
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return clkr->val;
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}
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/**
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* _read_divisor() - get current divisor applied to parent clock (from hdwr)
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* @clk: OMAP struct clk to use.
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*
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* Read the current divisor register value for @clk that is programmed
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* into the hardware, convert it into the actual divisor value, and
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* return it; or return 0 on error.
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*/
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static u32 _read_divisor(struct clk *clk)
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{
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u32 v;
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if (!clk->clksel || !clk->clksel_mask)
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return 0;
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v = __raw_readl(clk->clksel_reg);
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v &= clk->clksel_mask;
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v >>= __ffs(clk->clksel_mask);
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return _clksel_to_divisor(clk, v);
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}
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/* Public functions */
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/**
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* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
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* @clk: OMAP clock struct ptr to use
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*
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* Given a pointer to a source-selectable struct clk, read the hardware
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* register and determine what its parent is currently set to. Update the
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* clk->parent field with the appropriate clk ptr.
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*/
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void omap2_init_clksel_parent(struct clk *clk)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 r, found = 0;
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if (!clk->clksel)
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return;
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r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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r >>= __ffs(clk->clksel_mask);
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for (clks = clk->clksel; clks->parent && !found; clks++) {
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for (clkr = clks->rates; clkr->div && !found; clkr++) {
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if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
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if (clk->parent != clks->parent) {
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pr_debug("clock: inited %s parent "
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"to %s (was %s)\n",
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clk->name, clks->parent->name,
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((clk->parent) ?
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clk->parent->name : "NULL"));
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clk_reparent(clk, clks->parent);
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};
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found = 1;
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}
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}
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}
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if (!found)
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printk(KERN_ERR "clock: init parent: could not find "
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"regval %0x for clock %s\n", r, clk->name);
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return;
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}
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/*
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* Used for clocks that are part of CLKSEL_xyz governed clocks.
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* REVISIT: Maybe change to use clk->enable() functions like on omap1?
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*/
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unsigned long omap2_clksel_recalc(struct clk *clk)
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{
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unsigned long rate;
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u32 div = 0;
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pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
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div = omap2_clksel_get_divisor(clk);
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if (div == 0)
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return clk->rate;
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rate = clk->parent->rate / div;
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pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
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return rate;
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}
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/**
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* omap2_clksel_round_rate_div - find divisor for the given clock and rate
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* omap2_clksel_round_rate_div() - find divisor for the given clock and rate
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* @clk: OMAP struct clk to use
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* @target_rate: desired clock rate
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* @new_div: ptr to where we should store the divisor
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*
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* Finds 'best' divider value in an array based on the source and target
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* rates. The divider array must be sorted with smallest divider first.
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* This function is also used by the DPLL3 M2 divider code.
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*
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* Returns the rounded clock rate or returns 0xffffffff on error.
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*/
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@ -211,12 +281,15 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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const struct clksel_rate *clkr;
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u32 last_div = 0;
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if (!clk->clksel || !clk->clksel_mask)
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return ~0;
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pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
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clk->name, target_rate);
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*new_div = 1;
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clks = _omap2_get_clksel_by_parent(clk, clk->parent);
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clks = _get_clksel_by_parent(clk, clk->parent);
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if (!clks)
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return ~0;
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@ -252,16 +325,92 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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return clk->parent->rate / clkr->div;
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}
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/*
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* Clocktype interface functions to the OMAP clock code
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* (i.e., those used in struct clk field function pointers, etc.)
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*/
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/**
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* omap2_clksel_round_rate - find rounded rate for the given clock and rate
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* omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
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* @clk: OMAP clock struct ptr to use
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*
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* Given a pointer @clk to a source-selectable struct clk, read the
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* hardware register and determine what its parent is currently set
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* to. Update @clk's .parent field with the appropriate clk ptr. No
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* return value.
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*/
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void omap2_init_clksel_parent(struct clk *clk)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 r, found = 0;
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if (!clk->clksel || !clk->clksel_mask)
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return;
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r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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r >>= __ffs(clk->clksel_mask);
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for (clks = clk->clksel; clks->parent && !found; clks++) {
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for (clkr = clks->rates; clkr->div && !found; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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if (clkr->val == r) {
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if (clk->parent != clks->parent) {
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pr_debug("clock: inited %s parent "
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"to %s (was %s)\n",
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clk->name, clks->parent->name,
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((clk->parent) ?
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clk->parent->name : "NULL"));
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clk_reparent(clk, clks->parent);
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};
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found = 1;
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}
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}
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}
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/* This indicates a data error */
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WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
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clk->name, r);
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return;
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}
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/**
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* omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
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* @clk: struct clk *
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*
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* This function is intended to be called only by the clock framework.
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* Each clksel clock should have its struct clk .recalc field set to this
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* function. Returns the clock's current rate, based on its parent's rate
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* and its current divisor setting in the hardware.
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*/
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unsigned long omap2_clksel_recalc(struct clk *clk)
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{
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unsigned long rate;
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u32 div = 0;
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div = _read_divisor(clk);
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if (div == 0)
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return clk->rate;
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rate = clk->parent->rate / div;
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pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
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rate, div);
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return rate;
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}
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/**
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* omap2_clksel_round_rate() - find rounded rate for the given clock and rate
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* @clk: OMAP struct clk to use
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* @target_rate: desired clock rate
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*
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* Compatibility wrapper for OMAP clock framework
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* This function is intended to be called only by the clock framework.
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* Finds best target rate based on the source clock and possible dividers.
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* rates. The divider array must be sorted with smallest divider first.
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* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
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* they are only settable as part of virtual_prcm set.
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*
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* Returns the rounded clock rate or returns 0xffffffff on error.
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*/
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@ -272,148 +421,78 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
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return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
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}
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|
||||
/* Given a clock and a rate apply a clock specific rounding function */
|
||||
long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (clk->round_rate)
|
||||
return clk->round_rate(clk, rate);
|
||||
|
||||
return clk->rate;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_clksel_to_divisor() - turn clksel field value into integer divider
|
||||
* @clk: OMAP struct clk to use
|
||||
* @field_val: register field value to find
|
||||
* omap2_clksel_set_rate() - program clock rate in hardware
|
||||
* @clk: struct clk * to program rate
|
||||
* @rate: target rate to program
|
||||
*
|
||||
* Given a struct clk of a rate-selectable clksel clock, and a register field
|
||||
* value to search for, find the corresponding clock divisor. The register
|
||||
* field value should be pre-masked and shifted down so the LSB is at bit 0
|
||||
* before calling. Returns 0 on error
|
||||
* This function is intended to be called only by the clock framework.
|
||||
* Program @clk's rate to @rate in the hardware. The clock can be
|
||||
* either enabled or disabled when this happens, although if the clock
|
||||
* is enabled, some downstream devices may glitch or behave
|
||||
* unpredictably when the clock rate is changed - this depends on the
|
||||
* hardware. This function does not currently check the usecount of
|
||||
* the clock, so if multiple drivers are using the clock, and the rate
|
||||
* is changed, they will all be affected without any notification.
|
||||
* Returns -EINVAL upon error, or 0 upon success.
|
||||
*/
|
||||
u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
|
||||
{
|
||||
const struct clksel *clks;
|
||||
const struct clksel_rate *clkr;
|
||||
|
||||
clks = _omap2_get_clksel_by_parent(clk, clk->parent);
|
||||
if (!clks)
|
||||
return 0;
|
||||
|
||||
for (clkr = clks->rates; clkr->div; clkr++) {
|
||||
if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
|
||||
break;
|
||||
}
|
||||
|
||||
if (!clkr->div) {
|
||||
printk(KERN_ERR "clock: Could not find fieldval %d for "
|
||||
"clock %s parent %s\n", field_val, clk->name,
|
||||
clk->parent->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return clkr->div;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
|
||||
* @clk: OMAP struct clk to use
|
||||
* @div: integer divisor to search for
|
||||
*
|
||||
* Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
|
||||
* find the corresponding register field value. The return register value is
|
||||
* the value before left-shifting. Returns ~0 on error
|
||||
*/
|
||||
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
|
||||
{
|
||||
const struct clksel *clks;
|
||||
const struct clksel_rate *clkr;
|
||||
|
||||
/* should never happen */
|
||||
WARN_ON(div == 0);
|
||||
|
||||
clks = _omap2_get_clksel_by_parent(clk, clk->parent);
|
||||
if (!clks)
|
||||
return ~0;
|
||||
|
||||
for (clkr = clks->rates; clkr->div; clkr++) {
|
||||
if ((clkr->flags & cpu_mask) && (clkr->div == div))
|
||||
break;
|
||||
}
|
||||
|
||||
if (!clkr->div) {
|
||||
printk(KERN_ERR "clock: Could not find divisor %d for "
|
||||
"clock %s parent %s\n", div, clk->name,
|
||||
clk->parent->name);
|
||||
return ~0;
|
||||
}
|
||||
|
||||
return clkr->val;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_clksel_get_divisor - get current divider applied to parent clock.
|
||||
* @clk: OMAP struct clk to use.
|
||||
*
|
||||
* Returns the integer divisor upon success or 0 on error.
|
||||
*/
|
||||
u32 omap2_clksel_get_divisor(struct clk *clk)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (!clk->clksel_mask)
|
||||
return 0;
|
||||
|
||||
v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
|
||||
v >>= __ffs(clk->clksel_mask);
|
||||
|
||||
return omap2_clksel_to_divisor(clk, v);
|
||||
}
|
||||
|
||||
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 v, field_val, validrate, new_div = 0;
|
||||
u32 field_val, validrate, new_div = 0;
|
||||
|
||||
if (!clk->clksel_mask)
|
||||
if (!clk->clksel || !clk->clksel_mask)
|
||||
return -EINVAL;
|
||||
|
||||
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
|
||||
if (validrate != rate)
|
||||
return -EINVAL;
|
||||
|
||||
field_val = omap2_divisor_to_clksel(clk, new_div);
|
||||
field_val = _divisor_to_clksel(clk, new_div);
|
||||
if (field_val == ~0)
|
||||
return -EINVAL;
|
||||
|
||||
v = __raw_readl(clk->clksel_reg);
|
||||
v &= ~clk->clksel_mask;
|
||||
v |= field_val << __ffs(clk->clksel_mask);
|
||||
__raw_writel(v, clk->clksel_reg);
|
||||
v = __raw_readl(clk->clksel_reg); /* OCP barrier */
|
||||
_write_clksel_reg(clk, field_val);
|
||||
|
||||
clk->rate = clk->parent->rate / new_div;
|
||||
|
||||
pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Clksel parent setting function - not passed in struct clk function
|
||||
* pointer - instead, the OMAP clock code currently assumes that any
|
||||
* parent-setting clock is a clksel clock, and calls
|
||||
* omap2_clksel_set_parent() by default
|
||||
*/
|
||||
|
||||
/**
|
||||
* omap2_clksel_set_parent() - change a clock's parent clock
|
||||
* @clk: struct clk * of the child clock
|
||||
* @new_parent: struct clk * of the new parent clock
|
||||
*
|
||||
* This function is intended to be called only by the clock framework.
|
||||
* Change the parent clock of clock @clk to @new_parent. This is
|
||||
* intended to be used while @clk is disabled. This function does not
|
||||
* currently check the usecount of the clock, so if multiple drivers
|
||||
* are using the clock, and the parent is changed, they will all be
|
||||
* affected without any notification. Returns -EINVAL upon error, or
|
||||
* 0 upon success.
|
||||
*/
|
||||
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
|
||||
{
|
||||
u32 field_val, v, parent_div;
|
||||
u32 field_val = 0;
|
||||
u32 parent_div;
|
||||
|
||||
if (!clk->clksel || !clk->clksel_mask)
|
||||
return -EINVAL;
|
||||
|
||||
parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
|
||||
parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
|
||||
if (!parent_div)
|
||||
return -EINVAL;
|
||||
|
||||
/* Set new source value (previous dividers if any in effect) */
|
||||
v = __raw_readl(clk->clksel_reg);
|
||||
v &= ~clk->clksel_mask;
|
||||
v |= field_val << __ffs(clk->clksel_mask);
|
||||
__raw_writel(v, clk->clksel_reg);
|
||||
v = __raw_readl(clk->clksel_reg); /* OCP barrier */
|
||||
_write_clksel_reg(clk, field_val);
|
||||
|
||||
clk_reparent(clk, new_parent);
|
||||
|
||||
|
@ -423,7 +502,7 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
|
|||
if (parent_div > 0)
|
||||
clk->rate /= parent_div;
|
||||
|
||||
pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
|
||||
pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
|
||||
clk->name, clk->parent->name, clk->rate);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -334,6 +334,15 @@ int omap2_clk_enable(struct clk *clk)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Given a clock and a rate apply a clock specific rounding function */
|
||||
long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (clk->round_rate)
|
||||
return clk->round_rate(clk, rate);
|
||||
|
||||
return clk->rate;
|
||||
}
|
||||
|
||||
/* Set the clock rate for a clock source */
|
||||
int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
|
|
|
@ -73,19 +73,20 @@ void omap2_clk_disable_unused(struct clk *clk);
|
|||
#define omap2_clk_disable_unused NULL
|
||||
#endif
|
||||
|
||||
unsigned long omap2_clksel_recalc(struct clk *clk);
|
||||
void omap2_init_clk_clkdm(struct clk *clk);
|
||||
void omap2_init_clksel_parent(struct clk *clk);
|
||||
u32 omap2_clksel_get_divisor(struct clk *clk);
|
||||
|
||||
/* clkt_clksel.c public functions */
|
||||
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
||||
u32 *new_div);
|
||||
u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
|
||||
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
|
||||
void omap2_init_clksel_parent(struct clk *clk);
|
||||
unsigned long omap2_clksel_recalc(struct clk *clk);
|
||||
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
|
||||
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
|
||||
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
|
||||
|
||||
u32 omap2_get_dpll_rate(struct clk *clk);
|
||||
void omap2_init_dpll_parent(struct clk *clk);
|
||||
|
||||
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
|
||||
|
||||
|
||||
|
|
Loading…
Reference in a new issue