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drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets
All MG/DKL PHY register regions are evenly spaced offset-wise (0x168000, 0x169000, 0x16A000, 0x16B000) so the _MMIO_PORT() macro we use to access their registers only needs the first two offsets. We can drop the _PORT3 and _PORT4 offsets which are never directly referenced. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-12-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper
parent
24ce4d6d2c
commit
43571e15c0
1 changed files with 0 additions and 64 deletions
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@ -15,10 +15,6 @@
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#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
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#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
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#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
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#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
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#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
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#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
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#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
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#define MG_TX1_LINK_PARAMS(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
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MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
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@ -28,10 +24,6 @@
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#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
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#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
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#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
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#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
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#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
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#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
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#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
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#define MG_TX2_LINK_PARAMS(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
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MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
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@ -42,10 +34,6 @@
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#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
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#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
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#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
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#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
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#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
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#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
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#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
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#define MG_TX1_PISO_READLOAD(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
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MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
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@ -55,10 +43,6 @@
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#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
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#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
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#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
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#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
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#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
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#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
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#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
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#define MG_TX2_PISO_READLOAD(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
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MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
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@ -69,10 +53,6 @@
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#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
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#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
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#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
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#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
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#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
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#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
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#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
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#define MG_TX1_SWINGCTRL(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
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MG_TX_SWINGCTRL_TX1LN0_PORT2, \
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@ -82,10 +62,6 @@
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#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
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#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
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#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
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#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
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#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
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#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
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#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
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#define MG_TX2_SWINGCTRL(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
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MG_TX_SWINGCTRL_TX2LN0_PORT2, \
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@ -110,10 +86,6 @@
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#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
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#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
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#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
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#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
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#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
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#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
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#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
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#define MG_TX2_DRVCTRL(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
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MG_TX_DRVCTRL_TX2LN0_PORT2, \
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@ -130,10 +102,6 @@
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#define MG_CLKHUB_LN1_PORT1 0x16879C
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#define MG_CLKHUB_LN0_PORT2 0x16939C
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#define MG_CLKHUB_LN1_PORT2 0x16979C
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#define MG_CLKHUB_LN0_PORT3 0x16A39C
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#define MG_CLKHUB_LN1_PORT3 0x16A79C
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#define MG_CLKHUB_LN0_PORT4 0x16B39C
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#define MG_CLKHUB_LN1_PORT4 0x16B79C
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#define MG_CLKHUB(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
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MG_CLKHUB_LN0_PORT2, \
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@ -144,10 +112,6 @@
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#define MG_TX_DCC_TX1LN1_PORT1 0x168510
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#define MG_TX_DCC_TX1LN0_PORT2 0x169110
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#define MG_TX_DCC_TX1LN1_PORT2 0x169510
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#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
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#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
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#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
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#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
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#define MG_TX1_DCC(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
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MG_TX_DCC_TX1LN0_PORT2, \
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@ -156,10 +120,6 @@
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#define MG_TX_DCC_TX2LN1_PORT1 0x168490
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#define MG_TX_DCC_TX2LN0_PORT2 0x169090
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#define MG_TX_DCC_TX2LN1_PORT2 0x169490
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#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
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#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
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#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
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#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
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#define MG_TX2_DCC(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
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MG_TX_DCC_TX2LN0_PORT2, \
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@ -172,10 +132,6 @@
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#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
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#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
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#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
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#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
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#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
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#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
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#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
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#define MG_DP_MODE(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
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MG_DP_MODE_LN0_ACU_PORT2, \
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@ -200,8 +156,6 @@
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#define _MG_REFCLKIN_CTL_PORT1 0x16892C
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#define _MG_REFCLKIN_CTL_PORT2 0x16992C
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#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
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#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
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#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
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#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
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#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
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@ -210,8 +164,6 @@
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#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
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#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
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#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
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#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
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#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
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#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
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#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
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@ -222,8 +174,6 @@
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#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
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#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
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#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
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#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
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#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
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#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
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#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
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@ -242,8 +192,6 @@
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#define _MG_PLL_DIV0_PORT1 0x168A00
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#define _MG_PLL_DIV0_PORT2 0x169A00
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#define _MG_PLL_DIV0_PORT3 0x16AA00
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#define _MG_PLL_DIV0_PORT4 0x16BA00
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#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
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#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
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#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
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@ -255,8 +203,6 @@
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#define _MG_PLL_DIV1_PORT1 0x168A04
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#define _MG_PLL_DIV1_PORT2 0x169A04
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#define _MG_PLL_DIV1_PORT3 0x16AA04
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#define _MG_PLL_DIV1_PORT4 0x16BA04
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#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
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#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
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#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
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@ -270,8 +216,6 @@
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#define _MG_PLL_LF_PORT1 0x168A08
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#define _MG_PLL_LF_PORT2 0x169A08
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#define _MG_PLL_LF_PORT3 0x16AA08
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#define _MG_PLL_LF_PORT4 0x16BA08
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#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
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#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
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#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
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@ -283,8 +227,6 @@
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#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
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#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
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#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
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#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
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#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
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#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
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#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
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@ -297,8 +239,6 @@
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#define _MG_PLL_SSC_PORT1 0x168A10
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#define _MG_PLL_SSC_PORT2 0x169A10
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#define _MG_PLL_SSC_PORT3 0x16AA10
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#define _MG_PLL_SSC_PORT4 0x16BA10
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#define MG_PLL_SSC_EN (1 << 28)
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#define MG_PLL_SSC_TYPE(x) ((x) << 26)
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#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
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@ -310,8 +250,6 @@
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#define _MG_PLL_BIAS_PORT1 0x168A14
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#define _MG_PLL_BIAS_PORT2 0x169A14
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#define _MG_PLL_BIAS_PORT3 0x16AA14
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#define _MG_PLL_BIAS_PORT4 0x16BA14
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#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
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#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
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#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
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@ -330,8 +268,6 @@
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#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
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#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
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#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
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#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
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#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
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#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
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#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
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