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coresight-tpdm: Add integration test support 

Integration test for tpdm can help to generate the data for
verification of the topology during TPDM software bring up.

Sample:
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
cat /dev/tmc_etf0 > /data/etf-tpdm0.bin

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230117145708.16739-6-quic_jinlmao@quicinc.com
This commit is contained in:
Mao Jinlong 2023-01-17 06:57:04 -08:00 committed by Suzuki K Poulose
parent 1f00465d7f
commit 436cca9a2c
3 changed files with 81 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm Normal file
View File

@ -0,0 +1,13 @@
What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
Date: January 2023
KernelVersion 6.2
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
Description:
(Write) Run integration test for tpdm. Integration test
will generate test data for tpdm. It can help to make
sure that the trace path is enabled and the link configurations
are fine.
Accepts only one of the 2 values - 1 or 2.
1 : Generate 64 bits data
2 : Generate 32 bits data

54
drivers/hwtracing/coresight/coresight-tpdm.c
View File

@ -121,6 +121,59 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
/*
* value 1: 64 bits test data
* value 2: 32 bits test data
*/
static ssize_t integration_test_store(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t size)
{
int i, ret = 0;
unsigned long val;
struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
ret = kstrtoul(buf, 10, &val);
if (ret)
return ret;
if (val != 1 && val != 2)
return -EINVAL;
if (!drvdata->enable)
return -EINVAL;
if (val == 1)
val = ATBCNTRL_VAL_64;
else
val = ATBCNTRL_VAL_32;
CS_UNLOCK(drvdata->base);
writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
for (i = 0; i < INTEGRATION_TEST_CYCLE; i++)
writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
CS_LOCK(drvdata->base);
return size;
}
static DEVICE_ATTR_WO(integration_test);
static struct attribute *tpdm_attrs[] = {
&dev_attr_integration_test.attr,
NULL,
};
static struct attribute_group tpdm_attr_grp = {
.attrs = tpdm_attrs,
};
static const struct attribute_group *tpdm_attr_grps[] = {
&tpdm_attr_grp,
NULL,
};
static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
{
void __iomem *base;
@ -157,6 +210,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
desc.pdata = adev->dev.platform_data;
desc.dev = &adev->dev;
desc.access = CSDEV_ACCESS_IOMEM(base);
desc.groups = tpdm_attr_grps;
drvdata->csdev = coresight_register(&desc);
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);

14
drivers/hwtracing/coresight/coresight-tpdm.h
View File

@ -14,6 +14,20 @@
/* Enable bit for DSB subunit */
#define TPDM_DSB_CR_ENA BIT(0)
/* TPDM integration test registers */
#define TPDM_ITATBCNTRL (0xEF0)
#define TPDM_ITCNTRL (0xF00)
/* Register value for integration test */
#define ATBCNTRL_VAL_32 0xC00F1409
#define ATBCNTRL_VAL_64 0xC01F1409
/*
* Number of cycles to write value when
* integration test.
*/
#define INTEGRATION_TEST_CYCLE 10
/**
* The bits of PERIPHIDR0 register.
* The fields [6:0] of PERIPHIDR0 are used to determine what