ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi
The display pipeline has the same structure, resources and connections
on both the A23 and A33. The differences include:
- compatible strings
- extra clock, reset control, and IO region for SAT in the backend
only found on the A33
- missing ch1 clock for the TCON
However, while the A23 has the TCON ch1 clock defined in the CCU, and
the channel 1 registers are available, it does not have any means to
use channel 1 due to a lack of downstream encoders, and the enable bit
for channel 1 is hard-wired to 0 (off).
As the MIPI DSI output device is not officially documented, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Chen-Yu Tsai
Maxime Ripard
parent
d027521497
commit
437262c0db
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@ -68,6 +68,12 @@
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};
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};
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de: display-engine {
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/* compatible gets set in SoC specific dtsi file */
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allwinner,pipelines = <&fe0>;
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status = "disabled";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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@ -168,6 +174,42 @@
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#size-cells = <0>;
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};
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tcon0: lcd-controller@1c0c000 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01c0c000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_LCD>,
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<&ccu CLK_LCD_CH0>;
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clock-names = "ahb",
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"tcon-ch0";
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clock-output-names = "tcon-pixel-clock";
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resets = <&ccu RST_BUS_LCD>;
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reset-names = "lcd";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -570,6 +612,111 @@
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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fe0: display-frontend@1e00000 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01e00000 0x20000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
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<&ccu CLK_DRAM_DE_FE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_BUS_DE_FE>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@1e60000 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01e60000 0x10000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_BUS_DE_BE>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_in_be0>;
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};
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};
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};
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};
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drc0: drc@1e70000 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01e70000 0x10000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
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<&ccu CLK_DRAM_DRC>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_DRC>;
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assigned-clocks = <&ccu CLK_DRC>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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drc0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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drc0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_drc0>;
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};
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};
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drc0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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drc0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_drc0>;
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};
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};
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};
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};
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rtc: rtc@1f00000 {
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compatible = "allwinner,sun8i-a23-rtc";
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reg = <0x01f00000 0x400>;
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@ -159,12 +159,6 @@
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};
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};
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de: display-engine {
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compatible = "allwinner,sun8i-a33-display-engine";
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allwinner,pipelines = <&fe0>;
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status = "disabled";
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&ths>;
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@ -209,47 +203,6 @@
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};
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soc {
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tcon0: lcd-controller@1c0c000 {
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compatible = "allwinner,sun8i-a33-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_LCD>,
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<&ccu CLK_LCD_CH0>;
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clock-names = "ahb",
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"tcon-ch0";
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clock-output-names = "tcon-pixel-clock";
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resets = <&ccu RST_BUS_LCD>;
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reset-names = "lcd";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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tcon0_out_dsi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dsi_in_tcon0>;
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};
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun8i-a33-video-engine";
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reg = <0x01c0e000 0x1000>;
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@ -339,115 +292,6 @@
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status = "disabled";
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#phy-cells = <0>;
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};
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fe0: display-frontend@1e00000 {
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compatible = "allwinner,sun8i-a33-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
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<&ccu CLK_DRAM_DE_FE>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_BUS_DE_FE>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@1e60000 {
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compatible = "allwinner,sun8i-a33-display-backend";
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reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
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reg-names = "be", "sat";
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
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clock-names = "ahb", "mod",
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"ram", "sat";
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resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
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reset-names = "be", "sat";
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assigned-clocks = <&ccu CLK_DE_BE>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_in_be0>;
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};
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};
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};
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};
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drc0: drc@1e70000 {
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compatible = "allwinner,sun8i-a33-drc";
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reg = <0x01e70000 0x10000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
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<&ccu CLK_DRAM_DRC>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_DRC>;
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assigned-clocks = <&ccu CLK_DRC>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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drc0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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drc0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_drc0>;
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};
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};
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drc0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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drc0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_drc0>;
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};
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};
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};
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};
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};
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thermal-zones {
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@ -524,10 +368,37 @@
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};
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};
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&be0 {
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compatible = "allwinner,sun8i-a33-display-backend";
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/* A33 has an extra "SAT" module packed inside the display backend */
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reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
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reg-names = "be", "sat";
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clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
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clock-names = "ahb", "mod",
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"ram", "sat";
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resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
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reset-names = "be", "sat";
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assigned-clocks = <&ccu CLK_DE_BE>;
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assigned-clock-rates = <300000000>;
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};
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&ccu {
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compatible = "allwinner,sun8i-a33-ccu";
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};
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&de {
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compatible = "allwinner,sun8i-a33-display-engine";
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};
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&drc0 {
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compatible = "allwinner,sun8i-a33-drc";
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};
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&fe0 {
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compatible = "allwinner,sun8i-a33-display-frontend";
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};
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&mali {
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operating-points-v2 = <&mali_opp_table>;
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};
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@ -544,6 +415,17 @@
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};
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&tcon0 {
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compatible = "allwinner,sun8i-a33-tcon";
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};
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&tcon0_out {
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tcon0_out_dsi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dsi_in_tcon0>;
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};
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};
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&usb_otg {
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compatible = "allwinner,sun8i-a33-musb";
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};
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