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iommu/tegra-smmu: Fix invalid ASID bits on Tegra30/114
Both Tegra30 and Tegra114 have 4 ASID's and the corresponding bitfield of the TLB_FLUSH register differs from later Tegra generations that have 128 ASID's. In a result the PTE's are now flushed correctly from TLB and this fixes problems with graphics (randomly failing tests) on Tegra30. Cc: stable <stable@vger.kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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15ade5d2e7
commit
43a0541e31
1 changed files with 18 additions and 7 deletions
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@ -102,7 +102,6 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
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#define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
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#define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
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#define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
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#define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24)
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#define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
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SMMU_TLB_FLUSH_VA_MATCH_SECTION)
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#define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
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@ -205,8 +204,12 @@ static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
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{
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u32 value;
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value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
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SMMU_TLB_FLUSH_VA_MATCH_ALL;
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if (smmu->soc->num_asids == 4)
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value = (asid & 0x3) << 29;
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else
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value = (asid & 0x7f) << 24;
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value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
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smmu_writel(smmu, value, SMMU_TLB_FLUSH);
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}
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@ -216,8 +219,12 @@ static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
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{
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u32 value;
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value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
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SMMU_TLB_FLUSH_VA_SECTION(iova);
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if (smmu->soc->num_asids == 4)
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value = (asid & 0x3) << 29;
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else
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value = (asid & 0x7f) << 24;
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value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
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smmu_writel(smmu, value, SMMU_TLB_FLUSH);
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}
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@ -227,8 +234,12 @@ static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
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{
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u32 value;
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value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
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SMMU_TLB_FLUSH_VA_GROUP(iova);
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if (smmu->soc->num_asids == 4)
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value = (asid & 0x3) << 29;
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else
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value = (asid & 0x7f) << 24;
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value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
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smmu_writel(smmu, value, SMMU_TLB_FLUSH);
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}
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