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drm/amdgpu: Return error if no RAS
In amdgpu_ras_query_error_count() return an error
if the device doesn't support RAS. This prevents
that function from having to always set the values
of the integer pointers (if set), and thus
prevents function side effects--always to have to
set values of integers if integer pointers set,
regardless of whether RAS is supported or
not--with this change this side effect is
mitigated.
Also, if no pointers are set, don't count, since
we've no way of reporting the counts.
Also, give this function a kernel-doc.
Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Cc: John Clements <john.clements@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Reported-by: Tom Rix <trix@redhat.com>
Fixes: a46751fbcd
("drm/amdgpu: Fix RAS function interface")
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
798c511548
commit
43a44c5322
2 changed files with 38 additions and 17 deletions
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@ -809,7 +809,7 @@ static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
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/* query/inject/cure begin */
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/* query/inject/cure begin */
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int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
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int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
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struct ras_query_if *info)
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struct ras_query_if *info)
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{
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{
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struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
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struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
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struct ras_err_data err_data = {0, 0, 0, NULL};
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struct ras_err_data err_data = {0, 0, 0, NULL};
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@ -1043,17 +1043,32 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
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return ret;
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return ret;
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}
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}
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/* get the total error counts on all IPs */
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/**
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void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
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* amdgpu_ras_query_error_count -- Get error counts of all IPs
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unsigned long *ce_count,
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* adev: pointer to AMD GPU device
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unsigned long *ue_count)
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* ce_count: pointer to an integer to be set to the count of correctible errors.
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* ue_count: pointer to an integer to be set to the count of uncorrectible
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* errors.
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*
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* If set, @ce_count or @ue_count, count and return the corresponding
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* error counts in those integer pointers. Return 0 if the device
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* supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
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*/
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int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
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unsigned long *ce_count,
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unsigned long *ue_count)
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{
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj;
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struct ras_manager *obj;
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unsigned long ce, ue;
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unsigned long ce, ue;
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if (!adev->ras_enabled || !con)
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if (!adev->ras_enabled || !con)
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return;
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return -EOPNOTSUPP;
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/* Don't count since no reporting.
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*/
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if (!ce_count && !ue_count)
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return 0;
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ce = 0;
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ce = 0;
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ue = 0;
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ue = 0;
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@ -1061,9 +1076,11 @@ void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
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struct ras_query_if info = {
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struct ras_query_if info = {
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.head = obj->head,
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.head = obj->head,
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};
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};
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int res;
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if (amdgpu_ras_query_error_status(adev, &info))
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res = amdgpu_ras_query_error_status(adev, &info);
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return;
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if (res)
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return res;
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ce += info.ce_count;
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ce += info.ce_count;
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ue += info.ue_count;
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ue += info.ue_count;
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@ -1074,6 +1091,8 @@ void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
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if (ue_count)
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if (ue_count)
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*ue_count = ue;
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*ue_count = ue;
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return 0;
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}
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}
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/* query/inject/cure end */
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/* query/inject/cure end */
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@ -2137,9 +2156,10 @@ static void amdgpu_ras_counte_dw(struct work_struct *work)
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/* Cache new values.
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/* Cache new values.
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*/
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*/
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amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
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if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
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atomic_set(&con->ras_ce_count, ce_count);
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atomic_set(&con->ras_ce_count, ce_count);
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atomic_set(&con->ras_ue_count, ue_count);
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atomic_set(&con->ras_ue_count, ue_count);
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}
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pm_runtime_mark_last_busy(dev->dev);
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pm_runtime_mark_last_busy(dev->dev);
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Out:
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Out:
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@ -2312,9 +2332,10 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
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/* Those are the cached values at init.
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/* Those are the cached values at init.
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*/
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*/
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amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
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if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
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atomic_set(&con->ras_ce_count, ce_count);
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atomic_set(&con->ras_ce_count, ce_count);
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atomic_set(&con->ras_ue_count, ue_count);
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atomic_set(&con->ras_ue_count, ue_count);
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}
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return 0;
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return 0;
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cleanup:
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cleanup:
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@ -490,9 +490,9 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
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void amdgpu_ras_resume(struct amdgpu_device *adev);
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void amdgpu_ras_resume(struct amdgpu_device *adev);
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void amdgpu_ras_suspend(struct amdgpu_device *adev);
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void amdgpu_ras_suspend(struct amdgpu_device *adev);
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void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
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int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
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unsigned long *ce_count,
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unsigned long *ce_count,
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unsigned long *ue_count);
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unsigned long *ue_count);
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/* error handling functions */
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/* error handling functions */
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int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
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int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
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