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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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x86/irq: Move irq_cfg.irq_2_pin into io_apic.c
Now only io_apic.c accesses struct irq_cfg.irq_2_pin, so move irq_2_pin into struct mp_chip_data in io_apic.c to clean up struct irq_cfg further. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Tested-by: Joerg Roedel <jroedel@suse.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Grant Likely <grant.likely@linaro.org> Link: http://lkml.kernel.org/r/1428978610-28986-17-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
parent
9c72496698
commit
4467715a44
3 changed files with 78 additions and 98 deletions
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@ -176,13 +176,6 @@ struct irq_cfg {
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unsigned int dest_apicid;
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u8 vector;
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u8 move_in_progress : 1;
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union {
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#ifdef CONFIG_X86_IO_APIC
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struct {
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struct list_head irq_2_pin;
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};
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#endif
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};
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};
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extern struct irq_domain *x86_vector_domain;
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@ -78,7 +78,13 @@ static DEFINE_MUTEX(ioapic_mutex);
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static unsigned int ioapic_dynirq_base;
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static int ioapic_initialized;
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struct irq_pin_list {
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struct list_head list;
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int apic, pin;
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};
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struct mp_chip_data {
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struct list_head irq_2_pin;
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struct IO_APIC_route_entry entry;
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int trigger;
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int polarity;
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@ -215,16 +221,6 @@ void mp_save_irq(struct mpc_intsrc *m)
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panic("Max # of irq sources exceeded!!\n");
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}
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struct irq_pin_list {
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struct list_head list;
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int apic, pin;
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};
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static struct irq_pin_list *alloc_irq_pin_list(int node)
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{
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return kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
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}
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static void alloc_ioapic_saved_registers(int idx)
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{
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size_t size;
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@ -379,16 +375,17 @@ static void ioapic_mask_entry(int apic, int pin)
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* shared ISA-space IRQs, so we have to support them. We are super
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* fast in the common case, and fast for shared ISA-space IRQs.
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*/
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static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
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static int __add_pin_to_irq_node(struct mp_chip_data *data,
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int node, int apic, int pin)
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{
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struct irq_pin_list *entry;
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/* don't allow duplicates */
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for_each_irq_pin(entry, cfg->irq_2_pin)
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for_each_irq_pin(entry, data->irq_2_pin)
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if (entry->apic == apic && entry->pin == pin)
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return 0;
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entry = alloc_irq_pin_list(node);
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entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
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if (!entry) {
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pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
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node, apic, pin);
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@ -396,16 +393,16 @@ static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pi
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}
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entry->apic = apic;
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entry->pin = pin;
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list_add_tail(&entry->list, &data->irq_2_pin);
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list_add_tail(&entry->list, &cfg->irq_2_pin);
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return 0;
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}
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static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
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static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
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{
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struct irq_pin_list *tmp, *entry;
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list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list)
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list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
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if (entry->apic == apic && entry->pin == pin) {
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list_del(&entry->list);
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kfree(entry);
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@ -413,22 +410,23 @@ static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
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}
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}
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static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
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static void add_pin_to_irq_node(struct mp_chip_data *data,
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int node, int apic, int pin)
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{
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if (__add_pin_to_irq_node(cfg, node, apic, pin))
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if (__add_pin_to_irq_node(data, node, apic, pin))
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panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
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}
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/*
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* Reroute an IRQ to a different pin.
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*/
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static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
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static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
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int oldapic, int oldpin,
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int newapic, int newpin)
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{
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struct irq_pin_list *entry;
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for_each_irq_pin(entry, cfg->irq_2_pin) {
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for_each_irq_pin(entry, data->irq_2_pin) {
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if (entry->apic == oldapic && entry->pin == oldpin) {
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entry->apic = newapic;
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entry->pin = newpin;
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@ -438,7 +436,7 @@ static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
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}
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/* old apic/pin didn't exist, so just add new ones */
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add_pin_to_irq_node(cfg, node, newapic, newpin);
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add_pin_to_irq_node(data, node, newapic, newpin);
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}
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static void __io_apic_modify_irq(struct irq_pin_list *entry,
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@ -456,13 +454,13 @@ static void __io_apic_modify_irq(struct irq_pin_list *entry,
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final(entry);
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}
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static void io_apic_modify_irq(struct irq_cfg *cfg,
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static void io_apic_modify_irq(struct mp_chip_data *data,
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int mask_and, int mask_or,
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void (*final)(struct irq_pin_list *entry))
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{
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struct irq_pin_list *entry;
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for_each_irq_pin(entry, cfg->irq_2_pin)
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for_each_irq_pin(entry, data->irq_2_pin)
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__io_apic_modify_irq(entry, mask_and, mask_or, final);
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}
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@ -478,39 +476,31 @@ static void io_apic_sync(struct irq_pin_list *entry)
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readl(&io_apic->data);
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}
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static void mask_ioapic(struct irq_cfg *cfg)
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static void mask_ioapic_irq(struct irq_data *irq_data)
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{
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struct mp_chip_data *data = irq_data->chip_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
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io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void mask_ioapic_irq(struct irq_data *data)
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static void __unmask_ioapic(struct mp_chip_data *data)
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{
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mask_ioapic(irqd_cfg(data));
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io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
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}
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static void __unmask_ioapic(struct irq_cfg *cfg)
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{
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io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
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}
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static void unmask_ioapic(struct irq_cfg *cfg)
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static void unmask_ioapic_irq(struct irq_data *irq_data)
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{
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struct mp_chip_data *data = irq_data->chip_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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__unmask_ioapic(cfg);
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__unmask_ioapic(data);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void unmask_ioapic_irq(struct irq_data *data)
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{
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unmask_ioapic(irqd_cfg(data));
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}
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/*
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* IO-APIC versions below 0x20 don't support EOI register.
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* For the record, here is the information about various versions:
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@ -551,13 +541,13 @@ static void __eoi_ioapic_pin(int apic, int pin, int vector)
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}
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}
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void eoi_ioapic_pin(int vector, struct irq_cfg *cfg)
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void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
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{
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unsigned long flags;
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struct irq_pin_list *entry;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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for_each_irq_pin(entry, cfg->irq_2_pin)
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for_each_irq_pin(entry, data->irq_2_pin)
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__eoi_ioapic_pin(entry->apic, entry->pin, vector);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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@ -1068,11 +1058,10 @@ static int alloc_isa_irq_from_domain(struct irq_domain *domain,
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* entry. The IOAPIC entry
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*/
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if (irq_data && irq_data->parent_data) {
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struct irq_cfg *cfg = irqd_cfg(irq_data);
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if (!mp_check_pin_attr(irq, info))
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return -EBUSY;
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if (__add_pin_to_irq_node(cfg, node, ioapic, info->ioapic_pin))
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if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
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info->ioapic_pin))
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return -ENOMEM;
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} else {
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irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true);
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@ -1394,9 +1383,7 @@ static void __init print_IO_APIC(int ioapic_idx)
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void __init print_IO_APICs(void)
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{
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int ioapic_idx;
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struct irq_cfg *cfg;
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unsigned int irq;
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struct irq_chip *chip;
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printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
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for_each_ioapic(ioapic_idx)
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printk(KERN_DEBUG "IRQ to pin mappings:\n");
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for_each_active_irq(irq) {
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struct irq_pin_list *entry;
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struct irq_chip *chip;
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struct mp_chip_data *data;
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chip = irq_get_chip(irq);
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if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
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continue;
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data = irq_get_chip_data(irq);
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if (!data)
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continue;
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if (list_empty(&data->irq_2_pin))
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continue;
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cfg = irq_cfg(irq);
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if (!cfg)
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continue;
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if (list_empty(&cfg->irq_2_pin))
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continue;
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printk(KERN_DEBUG "IRQ%d ", irq);
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for_each_irq_pin(entry, cfg->irq_2_pin)
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for_each_irq_pin(entry, data->irq_2_pin)
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pr_cont("-> %d:%d", entry->apic, entry->pin);
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pr_cont("\n");
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}
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@ -1740,7 +1729,7 @@ static unsigned int startup_ioapic_irq(struct irq_data *data)
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if (legacy_pic->irq_pending(irq))
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was_pending = 1;
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}
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__unmask_ioapic(irqd_cfg(data));
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__unmask_ioapic(data->chip_data);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return was_pending;
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@ -1755,13 +1744,15 @@ static unsigned int startup_ioapic_irq(struct irq_data *data)
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* races.
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*/
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static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
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static void __target_IO_APIC_irq(unsigned int irq, struct irq_cfg *cfg,
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struct mp_chip_data *data)
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{
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int apic, pin;
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struct irq_pin_list *entry;
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u8 vector = cfg->vector;
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unsigned int dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid);
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for_each_irq_pin(entry, cfg->irq_2_pin) {
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for_each_irq_pin(entry, data->irq_2_pin) {
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unsigned int reg;
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apic = entry->apic;
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@ -1778,13 +1769,13 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
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atomic_t irq_mis_count;
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#ifdef CONFIG_GENERIC_PENDING_IRQ
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static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
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static bool io_apic_level_ack_pending(struct mp_chip_data *data)
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{
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struct irq_pin_list *entry;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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for_each_irq_pin(entry, cfg->irq_2_pin) {
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for_each_irq_pin(entry, data->irq_2_pin) {
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unsigned int reg;
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int pin;
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@ -1801,18 +1792,17 @@ static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
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return false;
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}
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static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
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static inline bool ioapic_irqd_mask(struct irq_data *data)
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{
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/* If we are moving the irq we need to mask it */
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if (unlikely(irqd_is_setaffinity_pending(data))) {
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mask_ioapic(cfg);
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mask_ioapic_irq(data);
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return true;
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}
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return false;
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}
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static inline void ioapic_irqd_unmask(struct irq_data *data,
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struct irq_cfg *cfg, bool masked)
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static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
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{
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if (unlikely(masked)) {
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/* Only migrate the irq if the ack has been received.
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@ -1841,31 +1831,30 @@ static inline void ioapic_irqd_unmask(struct irq_data *data,
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* accurate and is causing problems then it is a hardware bug
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* and you can go talk to the chipset vendor about it.
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*/
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if (!io_apic_level_ack_pending(cfg))
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if (!io_apic_level_ack_pending(data->chip_data))
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irq_move_masked_irq(data);
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unmask_ioapic(cfg);
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unmask_ioapic_irq(data);
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}
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}
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#else
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static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
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static inline bool ioapic_irqd_mask(struct irq_data *data)
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{
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return false;
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}
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static inline void ioapic_irqd_unmask(struct irq_data *data,
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struct irq_cfg *cfg, bool masked)
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static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
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{
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}
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#endif
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static void ioapic_ack_level(struct irq_data *data)
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static void ioapic_ack_level(struct irq_data *irq_data)
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{
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struct irq_cfg *cfg = irqd_cfg(data);
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struct irq_cfg *cfg = irqd_cfg(irq_data);
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unsigned long v;
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bool masked;
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int i;
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irq_complete_move(cfg);
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masked = ioapic_irqd_mask(data, cfg);
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masked = ioapic_irqd_mask(irq_data);
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/*
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* It appears there is an erratum which affects at least version 0x11
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@ -1917,10 +1906,10 @@ static void ioapic_ack_level(struct irq_data *data)
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*/
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if (!(v & (1 << (i & 0x1f)))) {
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atomic_inc(&irq_mis_count);
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eoi_ioapic_pin(cfg->vector, cfg);
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eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
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}
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ioapic_irqd_unmask(data, cfg, masked);
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ioapic_irqd_unmask(irq_data, masked);
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}
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static void ioapic_ir_ack_level(struct irq_data *irq_data)
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@ -1934,7 +1923,7 @@ static void ioapic_ir_ack_level(struct irq_data *irq_data)
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* EOI we use the pin number.
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*/
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ack_APIC_irq();
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eoi_ioapic_pin(data->entry.vector, irqd_cfg(irq_data));
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eoi_ioapic_pin(data->entry.vector, data);
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}
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static int ioapic_set_affinity(struct irq_data *irq_data,
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@ -1942,7 +1931,6 @@ static int ioapic_set_affinity(struct irq_data *irq_data,
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{
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struct irq_data *parent = irq_data->parent_data;
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struct mp_chip_data *data = irq_data->chip_data;
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unsigned int dest, irq = irq_data->irq;
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struct irq_cfg *cfg;
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unsigned long flags;
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int ret;
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@ -1953,9 +1941,7 @@ static int ioapic_set_affinity(struct irq_data *irq_data,
|
|||
cfg = irqd_cfg(irq_data);
|
||||
data->entry.dest = cfg->dest_apicid;
|
||||
data->entry.vector = cfg->vector;
|
||||
/* Only the high 8 bits are valid. */
|
||||
dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid);
|
||||
__target_IO_APIC_irq(irq, dest, cfg);
|
||||
__target_IO_APIC_irq(irq_data->irq, cfg, irq_data->chip_data);
|
||||
}
|
||||
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
|
||||
|
||||
|
@ -2116,10 +2102,11 @@ early_param("disable_timer_pin_1", disable_timer_pin_setup);
|
|||
static int mp_alloc_timer_irq(int ioapic, int pin)
|
||||
{
|
||||
int irq = -1;
|
||||
struct irq_alloc_info info;
|
||||
struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
|
||||
|
||||
if (domain) {
|
||||
struct irq_alloc_info info;
|
||||
|
||||
ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
|
||||
info.ioapic_id = mpc_ioapic_id(ioapic);
|
||||
info.ioapic_pin = pin;
|
||||
|
@ -2141,7 +2128,9 @@ static int mp_alloc_timer_irq(int ioapic, int pin)
|
|||
*/
|
||||
static inline void __init check_timer(void)
|
||||
{
|
||||
struct irq_cfg *cfg = irq_cfg(0);
|
||||
struct irq_data *irq_data = irq_get_irq_data(0);
|
||||
struct mp_chip_data *data = irq_data->chip_data;
|
||||
struct irq_cfg *cfg = irqd_cfg(irq_data);
|
||||
int node = cpu_to_node(0);
|
||||
int apic1, pin1, apic2, pin2;
|
||||
unsigned long flags;
|
||||
|
@ -2205,9 +2194,9 @@ static inline void __init check_timer(void)
|
|||
int idx;
|
||||
idx = find_irq_entry(apic1, pin1, mp_INT);
|
||||
if (idx != -1 && irq_trigger(idx))
|
||||
unmask_ioapic(cfg);
|
||||
unmask_ioapic_irq(irq_get_chip_data(0));
|
||||
}
|
||||
irq_domain_activate_irq(irq_get_irq_data(0));
|
||||
irq_domain_activate_irq(irq_data);
|
||||
if (timer_irq_works()) {
|
||||
if (disable_timer_pin_1 > 0)
|
||||
clear_IO_APIC_pin(0, pin1);
|
||||
|
@ -2227,8 +2216,8 @@ static inline void __init check_timer(void)
|
|||
/*
|
||||
* legacy devices should be connected to IO APIC #0
|
||||
*/
|
||||
replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
|
||||
irq_domain_activate_irq(irq_get_irq_data(0));
|
||||
replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
|
||||
irq_domain_activate_irq(irq_data);
|
||||
legacy_pic->unmask(0);
|
||||
if (timer_irq_works()) {
|
||||
apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
|
||||
|
@ -3044,6 +3033,7 @@ int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
|
|||
return ret;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&data->irq_2_pin);
|
||||
irq_data->hwirq = info->ioapic_pin;
|
||||
irq_data->chip = (domain->parent == x86_vector_domain) ?
|
||||
&ioapic_chip : &ioapic_ir_chip;
|
||||
|
@ -3051,7 +3041,7 @@ int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
|
|||
mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
|
||||
|
||||
cfg = irqd_cfg(irq_data);
|
||||
add_pin_to_irq_node(cfg, info->ioapic_node, ioapic, pin);
|
||||
add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
|
||||
if (info->ioapic_entry)
|
||||
mp_setup_entry(cfg, data, info->ioapic_entry);
|
||||
mp_register_handler(virq, data->trigger);
|
||||
|
@ -3069,15 +3059,16 @@ int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
|
|||
void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
|
||||
unsigned int nr_irqs)
|
||||
{
|
||||
struct irq_cfg *cfg = irq_cfg(virq);
|
||||
struct irq_data *irq_data;
|
||||
struct mp_chip_data *data;
|
||||
|
||||
BUG_ON(nr_irqs != 1);
|
||||
irq_data = irq_domain_get_irq_data(domain, virq);
|
||||
if (irq_data && irq_data->chip_data) {
|
||||
__remove_pin_from_irq(cfg, mp_irqdomain_ioapic_idx(domain),
|
||||
data = irq_data->chip_data;
|
||||
__remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
|
||||
(int)irq_data->hwirq);
|
||||
WARN_ON(!list_empty(&cfg->irq_2_pin));
|
||||
WARN_ON(!list_empty(&data->irq_2_pin));
|
||||
kfree(irq_data->chip_data);
|
||||
}
|
||||
irq_domain_free_irqs_top(domain, virq, nr_irqs);
|
||||
|
@ -3089,10 +3080,9 @@ void mp_irqdomain_activate(struct irq_domain *domain,
|
|||
unsigned long flags;
|
||||
struct irq_pin_list *entry;
|
||||
struct mp_chip_data *data = irq_data->chip_data;
|
||||
struct irq_cfg *cfg = irqd_cfg(irq_data);
|
||||
|
||||
raw_spin_lock_irqsave(&ioapic_lock, flags);
|
||||
for_each_irq_pin(entry, cfg->irq_2_pin)
|
||||
for_each_irq_pin(entry, data->irq_2_pin)
|
||||
__ioapic_write_entry(entry->apic, entry->pin, data->entry);
|
||||
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
|
||||
}
|
||||
|
|
|
@ -68,9 +68,6 @@ static struct irq_cfg *alloc_irq_cfg(int node)
|
|||
goto out_cfg;
|
||||
if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
|
||||
goto out_domain;
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
INIT_LIST_HEAD(&cfg->irq_2_pin);
|
||||
#endif
|
||||
return cfg;
|
||||
out_domain:
|
||||
free_cpumask_var(cfg->domain);
|
||||
|
|
Loading…
Reference in a new issue