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ASoC: tlv320aic32x4: Use correct shift definition for DATATYPE bits

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Setting the DATATYPE bit field requires shifting our value by 6. Setting
the J value of the PLL also requires a shift by 6. Currently the code
abuses this fact and uses the shift for the PLL register to set the
data-type register. Fix this here by using the definition meant for
this register.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andrew F. Davis 2017-12-12 16:43:05 -06:00 committed by Mark Brown
parent 7e2a4dc5c1
commit 4483521d81
No known key found for this signature in database
GPG key ID: 24D68B725D5487D0
1 changed files with 8 additions and 6 deletions
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14
sound/soc/codecs/tlv320aic32x4.c
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@ -641,21 +641,23 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_DSP_A:
iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
iface_reg_1 |= (AIC32X4_DSP_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
iface_reg_3 |= (1 << 3); /* invert bit clock */
iface_reg_2 = 0x01; /* add offset 1 */
break;
case SND_SOC_DAIFMT_DSP_B:
iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
iface_reg_1 |= (AIC32X4_DSP_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
iface_reg_3 |= (1 << 3); /* invert bit clock */
break;
case SND_SOC_DAIFMT_RIGHT_J:
iface_reg_1 |=
(AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
break;
case SND_SOC_DAIFMT_LEFT_J:
iface_reg_1 |=
(AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
AIC32X4_IFACE1_DATATYPE_SHIFT);
break;
default:
printk(KERN_ERR "aic32x4: invalid DAI interface format\n");