ASoC: add driver for Rockchip RK3xxx I2S controller
Add driver for i2s controller found on rk3066, rk3168 and rk3288 processors from rockchip. Tested on the RK3288 SDK board. Signed-off-by: Jianqun Xu <xjq@rock-chips.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Jianqun Xu
Mark Brown
parent
d4796e35fb
commit
4495c89fcf
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@ -47,6 +47,7 @@ source "sound/soc/kirkwood/Kconfig"
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source "sound/soc/intel/Kconfig"
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source "sound/soc/mxs/Kconfig"
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source "sound/soc/pxa/Kconfig"
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source "sound/soc/rockchip/Kconfig"
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source "sound/soc/samsung/Kconfig"
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source "sound/soc/s6000/Kconfig"
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source "sound/soc/sh/Kconfig"
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@ -24,6 +24,7 @@ obj-$(CONFIG_SND_SOC) += nuc900/
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obj-$(CONFIG_SND_SOC) += omap/
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obj-$(CONFIG_SND_SOC) += kirkwood/
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obj-$(CONFIG_SND_SOC) += pxa/
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obj-$(CONFIG_SND_SOC) += rockchip/
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obj-$(CONFIG_SND_SOC) += samsung/
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obj-$(CONFIG_SND_SOC) += s6000/
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obj-$(CONFIG_SND_SOC) += sh/
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@ -0,0 +1,12 @@
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config SND_SOC_ROCKCHIP
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tristate "ASoC support for Rockchip"
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depends on COMPILE_TEST || ARCH_ROCKCHIP
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select SND_SOC_GENERIC_DMAENGINE_PCM
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select SND_ROCKCHIP_I2S
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help
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Say Y or M if you want to add support for codecs attached to
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the Rockchip SoCs' Audio interfaces. You will also need to
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select the audio interfaces to support below.
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config SND_ROCKCHIP_I2S
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tristate
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@ -0,0 +1,4 @@
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# ROCKCHIP Platform Support
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snd-soc-i2s-objs := rockchip_i2s.o
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obj-$(CONFIG_SND_ROCKCHIP_I2S) += snd-soc-i2s.o
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@ -0,0 +1,530 @@
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/* sound/soc/rockchip/rockchip_i2s.c
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*
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* ALSA SoC Audio Layer - Rockchip I2S Controller driver
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*
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* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
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* Author: Jianqun <jay.xu@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/of_gpio.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include <sound/dmaengine_pcm.h>
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#include "rockchip_i2s.h"
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#define DRV_NAME "rockchip-i2s"
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struct rk_i2s_dev {
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struct device *dev;
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struct clk *hclk;
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struct clk *mclk;
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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struct regmap *regmap;
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/*
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* Used to indicate the tx/rx status.
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* I2S controller hopes to start the tx and rx together,
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* also to stop them when they are both try to stop.
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*/
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bool tx_start;
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bool rx_start;
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};
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static int i2s_runtime_suspend(struct device *dev)
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{
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struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
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clk_disable_unprepare(i2s->mclk);
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return 0;
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}
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static int i2s_runtime_resume(struct device *dev)
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{
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struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(i2s->mclk);
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if (ret) {
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dev_err(i2s->dev, "clock enable failed %d\n", ret);
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return ret;
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}
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return 0;
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}
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static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
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{
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return snd_soc_dai_get_drvdata(dai);
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}
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static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
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{
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unsigned int val = 0;
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int retry = 10;
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if (on) {
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regmap_update_bits(i2s->regmap, I2S_DMACR,
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I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START);
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i2s->tx_start = true;
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} else {
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i2s->tx_start = false;
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regmap_update_bits(i2s->regmap, I2S_DMACR,
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I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
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if (!i2s->rx_start) {
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START |
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I2S_XFER_RXS_START,
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I2S_XFER_TXS_STOP |
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I2S_XFER_RXS_STOP);
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regmap_update_bits(i2s->regmap, I2S_CLR,
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I2S_CLR_TXC | I2S_CLR_TXC,
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I2S_CLR_TXC | I2S_CLR_TXC);
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regmap_read(i2s->regmap, I2S_CLR, &val);
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/* Should wait for clear operation to finish */
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while (val) {
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regmap_read(i2s->regmap, I2S_CLR, &val);
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retry--;
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if (!retry)
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dev_warn(i2s->dev, "fail to clear\n");
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}
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}
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}
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}
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static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
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{
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unsigned int val = 0;
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int retry = 10;
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if (on) {
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regmap_update_bits(i2s->regmap, I2S_DMACR,
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I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START,
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I2S_XFER_TXS_START | I2S_XFER_RXS_START);
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i2s->rx_start = true;
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} else {
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i2s->rx_start = false;
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regmap_update_bits(i2s->regmap, I2S_DMACR,
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I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
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if (!i2s->tx_start) {
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regmap_update_bits(i2s->regmap, I2S_XFER,
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I2S_XFER_TXS_START |
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I2S_XFER_RXS_START,
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I2S_XFER_TXS_STOP |
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I2S_XFER_RXS_STOP);
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regmap_update_bits(i2s->regmap, I2S_CLR,
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I2S_CLR_TXC | I2S_CLR_TXC,
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I2S_CLR_TXC | I2S_CLR_TXC);
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regmap_read(i2s->regmap, I2S_CLR, &val);
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/* Should wait for clear operation to finish */
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while (val) {
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regmap_read(i2s->regmap, I2S_CLR, &val);
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retry--;
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if (!retry)
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dev_warn(i2s->dev, "fail to clear\n");
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}
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}
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}
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}
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static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct rk_i2s_dev *i2s = to_info(cpu_dai);
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unsigned int mask = 0, val = 0;
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mask = I2S_CKR_MSS_SLAVE;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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val = I2S_CKR_MSS_SLAVE;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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val = I2S_CKR_MSS_MASTER;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
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mask = I2S_TXCR_IBM_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_RIGHT_J:
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val = I2S_TXCR_IBM_RSJM;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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val = I2S_TXCR_IBM_LSJM;
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break;
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case SND_SOC_DAIFMT_I2S:
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val = I2S_TXCR_IBM_NORMAL;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
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mask = I2S_RXCR_IBM_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_RIGHT_J:
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val = I2S_RXCR_IBM_RSJM;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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val = I2S_RXCR_IBM_LSJM;
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break;
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case SND_SOC_DAIFMT_I2S:
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val = I2S_RXCR_IBM_NORMAL;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
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return 0;
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}
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static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct rk_i2s_dev *i2s = to_info(dai);
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unsigned int val = 0;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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val |= I2S_TXCR_VDW(8);
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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val |= I2S_TXCR_VDW(16);
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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val |= I2S_TXCR_VDW(20);
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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val |= I2S_TXCR_VDW(24);
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);
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regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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dai->playback_dma_data = &i2s->playback_dma_data;
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regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
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I2S_DMACR_TDL(1) | I2S_DMACR_TDE_ENABLE);
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} else {
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dai->capture_dma_data = &i2s->capture_dma_data;
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regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
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I2S_DMACR_RDL(1) | I2S_DMACR_RDE_ENABLE);
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}
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return 0;
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}
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static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct rk_i2s_dev *i2s = to_info(dai);
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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rockchip_snd_rxctrl(i2s, 1);
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else
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rockchip_snd_txctrl(i2s, 1);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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rockchip_snd_rxctrl(i2s, 0);
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else
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rockchip_snd_txctrl(i2s, 0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct rk_i2s_dev *i2s = to_info(cpu_dai);
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int ret;
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ret = clk_set_rate(i2s->mclk, freq);
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if (ret)
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dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
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return ret;
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}
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static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
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.hw_params = rockchip_i2s_hw_params,
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.set_sysclk = rockchip_i2s_set_sysclk,
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.set_fmt = rockchip_i2s_set_fmt,
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.trigger = rockchip_i2s_trigger,
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};
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static struct snd_soc_dai_driver rockchip_i2s_dai = {
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.playback = {
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.channels_min = 2,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = (SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S24_LE),
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},
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.capture = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = (SNDRV_PCM_FMTBIT_S8 |
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SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S24_LE),
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},
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.ops = &rockchip_i2s_dai_ops,
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};
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static const struct snd_soc_component_driver rockchip_i2s_component = {
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.name = DRV_NAME,
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};
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static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_TXCR:
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case I2S_RXCR:
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case I2S_CKR:
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case I2S_DMACR:
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case I2S_INTCR:
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case I2S_XFER:
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case I2S_CLR:
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case I2S_TXDR:
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return true;
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default:
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return false;
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}
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}
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static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_TXCR:
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case I2S_RXCR:
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case I2S_CKR:
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case I2S_DMACR:
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case I2S_INTCR:
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case I2S_XFER:
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case I2S_CLR:
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case I2S_RXDR:
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return true;
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default:
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return false;
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}
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}
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static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_FIFOLR:
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case I2S_INTSR:
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return true;
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default:
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return false;
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}
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}
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static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_FIFOLR:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config rockchip_i2s_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = I2S_RXDR,
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.writeable_reg = rockchip_i2s_wr_reg,
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.readable_reg = rockchip_i2s_rd_reg,
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.volatile_reg = rockchip_i2s_volatile_reg,
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.precious_reg = rockchip_i2s_precious_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static int rockchip_i2s_probe(struct platform_device *pdev)
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{
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struct rk_i2s_dev *i2s;
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struct resource *res;
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void __iomem *regs;
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int ret;
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i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
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if (!i2s) {
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dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
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return -ENOMEM;
|
||||
}
|
||||
|
||||
/* try to prepare related clocks */
|
||||
i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
|
||||
if (IS_ERR(i2s->hclk)) {
|
||||
dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
|
||||
return PTR_ERR(i2s->hclk);
|
||||
}
|
||||
|
||||
i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
|
||||
if (IS_ERR(i2s->mclk)) {
|
||||
dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
|
||||
return PTR_ERR(i2s->mclk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(regs)) {
|
||||
dev_err(&pdev->dev, "No memory resource\n");
|
||||
return PTR_ERR(regs);
|
||||
}
|
||||
|
||||
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
||||
&rockchip_i2s_regmap_config);
|
||||
if (IS_ERR(i2s->regmap)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Failed to initialise managed register map\n");
|
||||
return PTR_ERR(i2s->regmap);
|
||||
}
|
||||
|
||||
i2s->playback_dma_data.addr = res->start + I2S_TXDR;
|
||||
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
i2s->playback_dma_data.maxburst = 16;
|
||||
|
||||
i2s->capture_dma_data.addr = res->start + I2S_RXDR;
|
||||
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
i2s->capture_dma_data.maxburst = 16;
|
||||
|
||||
i2s->dev = &pdev->dev;
|
||||
dev_set_drvdata(&pdev->dev, i2s);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
if (!pm_runtime_enabled(&pdev->dev)) {
|
||||
ret = i2s_runtime_resume(&pdev->dev);
|
||||
if (ret)
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev,
|
||||
&rockchip_i2s_component,
|
||||
&rockchip_i2s_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register DAI\n");
|
||||
goto err_suspend;
|
||||
}
|
||||
|
||||
ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Could not register PCM\n");
|
||||
goto err_pcm_register;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_pcm_register:
|
||||
snd_dmaengine_pcm_unregister(&pdev->dev);
|
||||
err_suspend:
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
i2s_runtime_suspend(&pdev->dev);
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_i2s_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
if (!pm_runtime_status_suspended(&pdev->dev))
|
||||
i2s_runtime_suspend(&pdev->dev);
|
||||
|
||||
clk_disable_unprepare(i2s->mclk);
|
||||
clk_disable_unprepare(i2s->hclk);
|
||||
snd_dmaengine_pcm_unregister(&pdev->dev);
|
||||
snd_soc_unregister_component(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_i2s_match[] = {
|
||||
{ .compatible = "rockchip,rk3066-i2s", },
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct dev_pm_ops rockchip_i2s_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
|
||||
NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver rockchip_i2s_driver = {
|
||||
.probe = rockchip_i2s_probe,
|
||||
.remove = rockchip_i2s_remove,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(rockchip_i2s_match),
|
||||
.pm = &rockchip_i2s_pm_ops,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rockchip_i2s_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
|
||||
MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* sound/soc/rockchip/rockchip_i2s.h
|
||||
*
|
||||
* ALSA SoC Audio Layer - Rockchip I2S Controller driver
|
||||
*
|
||||
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
|
||||
* Author: Jianqun xu <jay.xu@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _ROCKCHIP_IIS_H
|
||||
#define _ROCKCHIP_IIS_H
|
||||
|
||||
/*
|
||||
* TXCR
|
||||
* transmit operation control register
|
||||
*/
|
||||
#define I2S_TXCR_RCNT_SHIFT 17
|
||||
#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
|
||||
#define I2S_TXCR_CSR_SHIFT 15
|
||||
#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
|
||||
#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
|
||||
#define I2S_TXCR_HWT BIT(14)
|
||||
#define I2S_TXCR_SJM_SHIFT 12
|
||||
#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
|
||||
#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
|
||||
#define I2S_TXCR_FBM_SHIFT 11
|
||||
#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
|
||||
#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_SHIFT 9
|
||||
#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
|
||||
#define I2S_TXCR_PBM_SHIFT 7
|
||||
#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
|
||||
#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
|
||||
#define I2S_TXCR_TFS_SHIFT 5
|
||||
#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
|
||||
#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
|
||||
#define I2S_TXCR_VDW_SHIFT 0
|
||||
#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
|
||||
#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
|
||||
|
||||
/*
|
||||
* RXCR
|
||||
* receive operation control register
|
||||
*/
|
||||
#define I2S_RXCR_HWT BIT(14)
|
||||
#define I2S_RXCR_SJM_SHIFT 12
|
||||
#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
|
||||
#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
|
||||
#define I2S_RXCR_FBM_SHIFT 11
|
||||
#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
|
||||
#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_SHIFT 9
|
||||
#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
|
||||
#define I2S_RXCR_PBM_SHIFT 7
|
||||
#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
|
||||
#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
|
||||
#define I2S_RXCR_TFS_SHIFT 5
|
||||
#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
|
||||
#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
|
||||
#define I2S_RXCR_VDW_SHIFT 0
|
||||
#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
|
||||
#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
|
||||
|
||||
/*
|
||||
* CKR
|
||||
* clock generation register
|
||||
*/
|
||||
#define I2S_CKR_MSS_SHIFT 27
|
||||
#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
|
||||
#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
|
||||
#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
|
||||
#define I2S_CKR_CKP_SHIFT 26
|
||||
#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
|
||||
#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
|
||||
#define I2S_CKR_RLP_SHIFT 25
|
||||
#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
|
||||
#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
|
||||
#define I2S_CKR_TLP_SHIFT 24
|
||||
#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
|
||||
#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
|
||||
#define I2S_CKR_MDIV_SHIFT 16
|
||||
#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)
|
||||
#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
|
||||
#define I2S_CKR_RSD_SHIFT 8
|
||||
#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)
|
||||
#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
|
||||
#define I2S_CKR_TSD_SHIFT 0
|
||||
#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)
|
||||
#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
|
||||
|
||||
/*
|
||||
* FIFOLR
|
||||
* FIFO level register
|
||||
*/
|
||||
#define I2S_FIFOLR_RFL_SHIFT 24
|
||||
#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
|
||||
#define I2S_FIFOLR_TFL3_SHIFT 18
|
||||
#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
|
||||
#define I2S_FIFOLR_TFL2_SHIFT 12
|
||||
#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
|
||||
#define I2S_FIFOLR_TFL1_SHIFT 6
|
||||
#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
|
||||
#define I2S_FIFOLR_TFL0_SHIFT 0
|
||||
#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
|
||||
|
||||
/*
|
||||
* DMACR
|
||||
* DMA control register
|
||||
*/
|
||||
#define I2S_DMACR_RDE_SHIFT 24
|
||||
#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
|
||||
#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
|
||||
#define I2S_DMACR_RDL_SHIFT 16
|
||||
#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
|
||||
#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
|
||||
#define I2S_DMACR_TDE_SHIFT 8
|
||||
#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
|
||||
#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
|
||||
#define I2S_DMACR_TDL_SHIFT 0
|
||||
#define I2S_DMACR_TDL(x) ((x - 1) << I2S_DMACR_TDL_SHIFT)
|
||||
#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
|
||||
|
||||
/*
|
||||
* INTCR
|
||||
* interrupt control register
|
||||
*/
|
||||
#define I2S_INTCR_RFT_SHIFT 20
|
||||
#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
|
||||
#define I2S_INTCR_RXOIC BIT(18)
|
||||
#define I2S_INTCR_RXOIE_SHIFT 17
|
||||
#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
|
||||
#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
|
||||
#define I2S_INTCR_RXFIE_SHIFT 16
|
||||
#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
|
||||
#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
|
||||
#define I2S_INTCR_TFT_SHIFT 4
|
||||
#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
|
||||
#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
|
||||
#define I2S_INTCR_TXUIC BIT(2)
|
||||
#define I2S_INTCR_TXUIE_SHIFT 1
|
||||
#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
|
||||
#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
|
||||
|
||||
/*
|
||||
* INTSR
|
||||
* interrupt status register
|
||||
*/
|
||||
#define I2S_INTSR_TXEIE_SHIFT 0
|
||||
#define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
|
||||
#define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
|
||||
#define I2S_INTSR_RXOI_SHIFT 17
|
||||
#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
|
||||
#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
|
||||
#define I2S_INTSR_RXFI_SHIFT 16
|
||||
#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
|
||||
#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
|
||||
#define I2S_INTSR_TXUI_SHIFT 1
|
||||
#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
|
||||
#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
|
||||
#define I2S_INTSR_TXEI_SHIFT 0
|
||||
#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
|
||||
#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
|
||||
|
||||
/*
|
||||
* XFER
|
||||
* Transfer start register
|
||||
*/
|
||||
#define I2S_XFER_RXS_SHIFT 1
|
||||
#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
|
||||
#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
|
||||
#define I2S_XFER_TXS_SHIFT 0
|
||||
#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
|
||||
#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
|
||||
|
||||
/*
|
||||
* CLR
|
||||
* clear SCLK domain logic register
|
||||
*/
|
||||
#define I2S_CLR_RXC BIT(1)
|
||||
#define I2S_CLR_TXC BIT(0)
|
||||
|
||||
/*
|
||||
* TXDR
|
||||
* Transimt FIFO data register, write only.
|
||||
*/
|
||||
#define I2S_TXDR_MASK (0xff)
|
||||
|
||||
/*
|
||||
* RXDR
|
||||
* Receive FIFO data register, write only.
|
||||
*/
|
||||
#define I2S_RXDR_MASK (0xff)
|
||||
|
||||
/* Clock divider id */
|
||||
enum {
|
||||
ROCKCHIP_DIV_MCLK = 0,
|
||||
ROCKCHIP_DIV_BCLK,
|
||||
};
|
||||
|
||||
/* I2S REGS */
|
||||
#define I2S_TXCR (0x0000)
|
||||
#define I2S_RXCR (0x0004)
|
||||
#define I2S_CKR (0x0008)
|
||||
#define I2S_FIFOLR (0x000c)
|
||||
#define I2S_DMACR (0x0010)
|
||||
#define I2S_INTCR (0x0014)
|
||||
#define I2S_INTSR (0x0018)
|
||||
#define I2S_XFER (0x001c)
|
||||
#define I2S_CLR (0x0020)
|
||||
#define I2S_TXDR (0x0024)
|
||||
#define I2S_RXDR (0x0028)
|
||||
|
||||
#endif /* _ROCKCHIP_IIS_H */
|
||||
Loading…
Reference in New Issue