From 44a374c0667df6b5de63266a4cf15f400827a29a Mon Sep 17 00:00:00 2001 From: Martin Schiller Date: Tue, 30 May 2017 06:34:34 +0200 Subject: [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks ASC1 is available on every Lantiq SoC (also AmazonSE) and should be enabled like the other generic xway clocks instead of ASC0, which is only available for AR9 and Danube. Signed-off-by: Martin Schiller Acked-by: Hauke Mehrtens Cc: Ralf Baechle Cc: John Crispin Cc: Arnd Bergmann Cc: Felix Fietkau Cc: Martin Schiller Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16145/ [jhogan@kernel.org: Drop braces] Signed-off-by: James Hogan --- arch/mips/lantiq/xway/sysctrl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index 7611c3013793..52500d3b7004 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -446,9 +446,9 @@ void __init ltq_soc_init(void) /* add our generic xway clocks */ clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI); - clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0); clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT); clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP); + clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA); clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI); clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU); @@ -462,10 +462,8 @@ void __init ltq_soc_init(void) clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE); } - if (!of_machine_is_compatible("lantiq,ase")) { - clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); + if (!of_machine_is_compatible("lantiq,ase")) clkdev_add_pci(); - } if (of_machine_is_compatible("lantiq,grx390") || of_machine_is_compatible("lantiq,ar10")) {