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staging: fsl-dpaa2/ethsw: Add Freescale DPAA2 Ethernet Switch driver

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Introduce the DPAA2 Ethernet Switch driver, which manages Datapath Switch
(DPSW) objects discovered on the MC bus.

Suggested-by: Alexandru Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Razvan Stefanescu 2018-03-14 10:55:54 -05:00 committed by Greg Kroah-Hartman
parent 0006351fd1
commit 44baaa43d7
3 changed files with 1573 additions and 1 deletions
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2
drivers/staging/fsl-dpaa2/ethsw/Makefile
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@ -7,4 +7,4 @@
obj-$(CONFIG_FSL_DPAA2_ETHSW) += dpaa2-ethsw.o
dpaa2-ethsw-objs := dpsw.o
dpaa2-ethsw-objs := ethsw.o dpsw.o

1507
drivers/staging/fsl-dpaa2/ethsw/ethsw.c Normal file
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File diff suppressed because it is too large Load diff

65
drivers/staging/fsl-dpaa2/ethsw/ethsw.h Normal file
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@ -0,0 +1,65 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DPAA2 Ethernet Switch declarations
*
* Copyright 2014-2016 Freescale Semiconductor Inc.
* Copyright 2017-2018 NXP
*
*/
#ifndef __ETHSW_H
#define __ETHSW_H
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/rtnetlink.h>
#include <linux/if_vlan.h>
#include <uapi/linux/if_bridge.h>
#include <net/switchdev.h>
#include <linux/if_bridge.h>
#include "dpsw.h"
/* Number of IRQs supported */
#define DPSW_IRQ_NUM 2
#define ETHSW_VLAN_MEMBER 1
#define ETHSW_VLAN_UNTAGGED 2
#define ETHSW_VLAN_PVID 4
#define ETHSW_VLAN_GLOBAL 8
/* Maximum Frame Length supported by HW (currently 10k) */
#define DPAA2_MFL (10 * 1024)
#define ETHSW_MAX_FRAME_LENGTH (DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN)
#define ETHSW_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN)
struct ethsw_core;
/* Per port private data */
struct ethsw_port_priv {
struct net_device *netdev;
u16 idx;
struct ethsw_core *ethsw_data;
u8 link_state;
u8 stp_state;
bool flood;
u8 vlans[VLAN_VID_MASK + 1];
u16 pvid;
struct net_device *bridge_dev;
};
/* Switch data */
struct ethsw_core {
struct device *dev;
struct fsl_mc_io *mc_io;
u16 dpsw_handle;
struct dpsw_attr sw_attr;
int dev_id;
struct ethsw_port_priv **ports;
u8 vlans[VLAN_VID_MASK + 1];
bool learning;
};
#endif /* __ETHSW_H */