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cxl: Convert find_cxl_root() to return a 'struct cxl_root *'
Commit 790815902e
("cxl: Add support for _DSM Function for retrieving QTG ID")
introduced 'struct cxl_root', however all usages have been worked
indirectly through cxl_port. Refactor code such as find_cxl_root()
function to use 'struct cxl_root' directly.
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/170449246044.3779673.13035770941393418591.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
parent
98856b2ea3
commit
44cd71ef7b
6 changed files with 28 additions and 23 deletions
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@ -295,14 +295,12 @@ cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
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return rc;
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return rc;
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}
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}
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static int cxl_acpi_qos_class(struct cxl_port *root_port,
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static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
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struct access_coordinate *coord, int entries,
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struct access_coordinate *coord, int entries,
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int *qos_class)
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int *qos_class)
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{
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{
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struct device *dev = cxl_root->port.uport_dev;
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acpi_handle handle;
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acpi_handle handle;
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struct device *dev;
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dev = root_port->uport_dev;
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if (!dev_is_platform(dev))
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if (!dev_is_platform(dev))
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return -ENODEV;
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return -ENODEV;
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@ -162,7 +162,6 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
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struct xarray *dsmas_xa)
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struct xarray *dsmas_xa)
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{
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{
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struct access_coordinate c;
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struct access_coordinate c;
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struct cxl_port *root_port;
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struct cxl_root *cxl_root;
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struct cxl_root *cxl_root;
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struct dsmas_entry *dent;
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struct dsmas_entry *dent;
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int valid_entries = 0;
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int valid_entries = 0;
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@ -175,8 +174,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
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return rc;
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return rc;
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}
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}
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root_port = find_cxl_root(port);
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cxl_root = find_cxl_root(port);
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cxl_root = to_cxl_root(root_port);
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if (!cxl_root->ops || !cxl_root->ops->qos_class)
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if (!cxl_root->ops || !cxl_root->ops->qos_class)
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return -EOPNOTSUPP;
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return -EOPNOTSUPP;
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@ -193,7 +191,8 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
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dent->coord.write_bandwidth);
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dent->coord.write_bandwidth);
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dent->entries = 1;
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dent->entries = 1;
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rc = cxl_root->ops->qos_class(root_port, &dent->coord, 1, &qos_class);
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rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1,
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&qos_class);
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if (rc != 1)
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if (rc != 1)
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continue;
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continue;
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@ -349,15 +348,19 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd)
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{
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{
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
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struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
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struct cxl_port *root_port __free(put_device) = NULL;
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LIST_HEAD(__discard);
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LIST_HEAD(__discard);
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struct list_head *discard __free(dpa_perf) = &__discard;
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struct list_head *discard __free(dpa_perf) = &__discard;
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struct cxl_port *root_port;
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int rc;
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int rc;
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root_port = find_cxl_root(cxlmd->endpoint);
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struct cxl_root *cxl_root __free(put_cxl_root) =
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if (!root_port)
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find_cxl_root(cxlmd->endpoint);
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if (!cxl_root)
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return -ENODEV;
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return -ENODEV;
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root_port = &cxl_root->port;
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/* Check that the QTG IDs are all sane between end device and root decoders */
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/* Check that the QTG IDs are all sane between end device and root decoders */
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cxl_qos_match(root_port, &mds->ram_perf_list, discard);
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cxl_qos_match(root_port, &mds->ram_perf_list, discard);
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cxl_qos_match(root_port, &mds->pmem_perf_list, discard);
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cxl_qos_match(root_port, &mds->pmem_perf_list, discard);
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@ -64,12 +64,14 @@ static int match_nvdimm_bridge(struct device *dev, void *data)
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd)
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd)
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{
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{
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struct cxl_port *port = find_cxl_root(cxlmd->endpoint);
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struct cxl_root *cxl_root = find_cxl_root(cxlmd->endpoint);
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struct cxl_port *port;
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struct device *dev;
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struct device *dev;
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if (!port)
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if (!cxl_root)
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return NULL;
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return NULL;
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port = &cxl_root->port;
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dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge);
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dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge);
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put_device(&port->dev);
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put_device(&port->dev);
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@ -972,7 +972,7 @@ static bool dev_is_cxl_root_child(struct device *dev)
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return false;
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return false;
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}
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}
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struct cxl_port *find_cxl_root(struct cxl_port *port)
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struct cxl_root *find_cxl_root(struct cxl_port *port)
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{
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{
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struct cxl_port *iter = port;
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struct cxl_port *iter = port;
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@ -982,7 +982,7 @@ struct cxl_port *find_cxl_root(struct cxl_port *port)
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if (!iter)
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if (!iter)
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return NULL;
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return NULL;
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get_device(&iter->dev);
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get_device(&iter->dev);
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return iter;
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return to_cxl_root(iter);
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}
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}
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EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL);
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EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL);
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@ -617,12 +617,6 @@ struct cxl_port {
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long pci_latency;
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long pci_latency;
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};
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};
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struct cxl_root_ops {
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int (*qos_class)(struct cxl_port *root_port,
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struct access_coordinate *coord, int entries,
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int *qos_class);
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};
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/**
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/**
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* struct cxl_root - logical collection of root cxl_port items
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* struct cxl_root - logical collection of root cxl_port items
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*
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*
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@ -640,6 +634,12 @@ to_cxl_root(const struct cxl_port *port)
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return container_of(port, struct cxl_root, port);
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return container_of(port, struct cxl_root, port);
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}
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}
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struct cxl_root_ops {
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int (*qos_class)(struct cxl_root *cxl_root,
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struct access_coordinate *coord, int entries,
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int *qos_class);
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};
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static inline struct cxl_dport *
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static inline struct cxl_dport *
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cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
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cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
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{
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{
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@ -734,7 +734,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host,
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struct cxl_dport *parent_dport);
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struct cxl_dport *parent_dport);
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struct cxl_root *devm_cxl_add_root(struct device *host,
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struct cxl_root *devm_cxl_add_root(struct device *host,
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const struct cxl_root_ops *ops);
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const struct cxl_root_ops *ops);
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struct cxl_port *find_cxl_root(struct cxl_port *port);
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struct cxl_root *find_cxl_root(struct cxl_port *port);
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void put_cxl_root(struct cxl_root *cxl_root);
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void put_cxl_root(struct cxl_root *cxl_root);
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DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))
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DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))
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@ -94,6 +94,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
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struct cxl_endpoint_dvsec_info info = { .port = port };
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struct cxl_endpoint_dvsec_info info = { .port = port };
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struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
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struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_dev_state *cxlds = cxlmd->cxlds;
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struct cxl_root *cxl_root;
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struct cxl_hdm *cxlhdm;
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struct cxl_hdm *cxlhdm;
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struct cxl_port *root;
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struct cxl_port *root;
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int rc;
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int rc;
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@ -130,7 +131,8 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
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* This can't fail in practice as CXL root exit unregisters all
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* This can't fail in practice as CXL root exit unregisters all
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* descendant ports and that in turn synchronizes with cxl_port_probe()
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* descendant ports and that in turn synchronizes with cxl_port_probe()
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*/
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*/
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root = find_cxl_root(port);
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cxl_root = find_cxl_root(port);
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root = &cxl_root->port;
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/*
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/*
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* Now that all endpoint decoders are successfully enumerated, try to
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* Now that all endpoint decoders are successfully enumerated, try to
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