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arm64: dts: rockchip: add rk3328 dwc3 usb controller node
RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Cameron Nemo <cnemo@tutanota.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210209192350.7130-7-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -980,6 +980,25 @@ usb_host0_ohci: usb@ff5d0000 {
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status = "disabled";
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};
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usbdrd3: usb@ff600000 {
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compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
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reg = <0x0 0xff600000 0x0 0x100000>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
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<&cru ACLK_USB3OTG>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk";
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dr_mode = "otg";
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phy_type = "utmi_wide";
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snps,dis-del-phy-power-chg-quirk;
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snps,dis_enblslpm_quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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status = "disabled";
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};
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gic: interrupt-controller@ff811000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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