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ARM: OMAP: Clean up interrupt lines to fix warnings for multi-omap
If boards with different NR_IRQS are compiled together, tons of compiler warnings are emitted about redefining NR_IRQS. This patch fixes the problem by adding up NR_IRQS in a common place. Patch also removes quite a bit of now unnecessary code. Signed-off-by: Tony Lindgren <tony@atomide.com>
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78673bc898
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7 changed files with 64 additions and 59 deletions
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@ -32,7 +32,7 @@
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static void fpga_mask_irq(unsigned int irq)
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{
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irq -= OMAP1510_IH_FPGA_BASE;
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irq -= OMAP_FPGA_IRQ_BASE;
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if (irq < 8)
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__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
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@ -65,7 +65,7 @@ static void fpga_ack_irq(unsigned int irq)
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static void fpga_unmask_irq(unsigned int irq)
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{
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irq -= OMAP1510_IH_FPGA_BASE;
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irq -= OMAP_FPGA_IRQ_BASE;
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if (irq < 8)
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__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
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@ -95,8 +95,8 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
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if (!stat)
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return;
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for (fpga_irq = OMAP1510_IH_FPGA_BASE;
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(fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
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for (fpga_irq = OMAP_FPGA_IRQ_BASE;
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(fpga_irq < OMAP_FPGA_IRQ_END) && stat;
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fpga_irq++, stat >>= 1) {
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if (stat & 1) {
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d = irq_desc + fpga_irq;
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@ -151,7 +151,7 @@ void omap1510_fpga_init_irq(void)
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__raw_writeb(0, OMAP1510_FPGA_IMR_HI);
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__raw_writeb(0, INNOVATOR_FPGA_IMR2);
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for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
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for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
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if (i == OMAP1510_INT_FPGA_TS) {
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/*
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@ -36,9 +36,4 @@
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#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
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/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
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#define IH_TWL4030_BASE IH_BOARD_BASE
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#define IH_TWL4030_END (IH_TWL4030_BASE+8)
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#define NR_IRQS (IH_TWL4030_END)
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#endif /* __ASM_ARCH_OMAP_2430SDP_H */
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@ -30,12 +30,6 @@
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/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
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#define OMAP1710_ETHR_START 0x04000300
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#define MAXIRQNUM (IH_BOARD_BASE)
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#define MAXFIQNUM MAXIRQNUM
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#define MAXSWINUM MAXIRQNUM
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#define NR_IRQS (MAXIRQNUM + 1)
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extern void h3_mmc_init(void);
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extern void h3_mmc_slot_cover_handler(void *arg, int state);
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@ -36,9 +36,6 @@
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#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
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#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
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#define NR_FPGA_IRQS 24
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#define NR_IRQS (IH_BOARD_BASE + NR_FPGA_IRQS)
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#ifndef __ASSEMBLY__
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void fpga_write(unsigned char val, int reg);
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unsigned char fpga_read(int reg);
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@ -36,10 +36,4 @@
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#define OMAP_SDRAM_DEVICE D256M_1X16_4B
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#endif
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#define MAXIRQNUM IH_BOARD_BASE
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#define MAXFIQNUM MAXIRQNUM
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#define MAXSWINUM MAXIRQNUM
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#define NR_IRQS (MAXIRQNUM + 1)
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#endif
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@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
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#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
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/* IRQ Numbers for interrupts muxed through the FPGA */
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#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
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#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)
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#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1)
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#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2)
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#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3)
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#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4)
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#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5)
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#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6)
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#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7)
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#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8)
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#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9)
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#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10)
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#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11)
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#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12)
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#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13)
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#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14)
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#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15)
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#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16)
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#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17)
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#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18)
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#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19)
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#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20)
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#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21)
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#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22)
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#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
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#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
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#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
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#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
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#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
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#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
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#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
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#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
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#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
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#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
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#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
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#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
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#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
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#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
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#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
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#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
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#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
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#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
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#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
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#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
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#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
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#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
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#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
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#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
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#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
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#endif
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@ -285,7 +285,41 @@
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#define OMAP_MAX_GPIO_LINES 192
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#define IH_GPIO_BASE (128 + IH2_BASE)
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#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
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#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
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#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
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/* External FPGA handles interrupts on Innovator boards */
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#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
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#ifdef CONFIG_MACH_OMAP_INNOVATOR
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#define OMAP_FPGA_NR_IRQS 24
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#else
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#define OMAP_FPGA_NR_IRQS 0
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#endif
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#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
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/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
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#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
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#ifdef CONFIG_TWL4030_CORE
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#define TWL4030_BASE_NR_IRQS 8
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#define TWL4030_PWR_NR_IRQS 8
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#else
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#define TWL4030_BASE_NR_IRQS 0
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#define TWL4030_PWR_NR_IRQS 0
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#endif
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#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
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#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
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#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
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/* External TWL4030 gpio interrupts are optional */
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#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
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#ifdef CONFIG_TWL4030_GPIO
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#define TWL4030_GPIO_NR_IRQS 18
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#else
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#define TWL4030_GPIO_NR_IRQS 0
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#endif
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#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
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/* Total number of interrupts depends on the enabled blocks above */
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#define NR_IRQS TWL4030_GPIO_IRQ_END
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#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
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extern void omap_init_irq(void);
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#endif
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/*
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* The definition of NR_IRQS is in board-specific header file, which is
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* included via hardware.h
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*/
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#include <asm/hardware.h>
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#ifndef NR_IRQS
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#define NR_IRQS IH_BOARD_BASE
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#endif
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#endif
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