mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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drm-misc-next for v6.5:
UAPI Changes: Cross-subsystem Changes: Core Changes: Driver Changes: * bridge * imx: Fix module linking * tc358762: Support reset GPIO * meson * Add support for MIPI DSI displays; plus fixes and DT bindings * panel * Add Support for Rocktech RK043FN48H; plus DT bindings * Add support for Starry himax83102-j02; plus DT bindings * Add support for Starry ili9882t; plus DT bindings * virtio * Support sync-object UAPI -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEchf7rIzpz2NEoWjlaA3BHVMLeiMFAmSARhUACgkQaA3BHVML eiMD2Qf+NRXLV0Gnvjn3z5Q8tTkWHhfVvSdL+tCqViTAYFxcqbdshNXGCI2hUNMO hzmfMb2Mcx4vYgMuvQgyUk+xSRGBS6anikEDP5YWRjwDGyY4sspf12rAolA/ZZSR yS1Gbwo16TaV+Nb+OEd02TPAN4Hki2lnmyiBdLDlqMvBzMmgsIq4lYkyeCA4L/8m +v9n6wJyWSQ4t3bKGHsI+OImBFCZR5RtTkXxw10RjE2ZnQr4roBPB/jrRVuFn9d0 vwzJjwTZqdc7PqW1VgWdG4pQ8m5beM1mqJGLNp4e7ICAABsjM9x6KqMW+HUb0nSp NLmuqu/gubfKrH29Mo92WRiQEkXBvA== =GRhf -----END PGP SIGNATURE----- Merge tag 'drm-misc-next-2023-06-07' of git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v6.5: UAPI Changes: Cross-subsystem Changes: Core Changes: Driver Changes: * bridge * imx: Fix module linking * tc358762: Support reset GPIO * meson * Add support for MIPI DSI displays; plus fixes and DT bindings * panel * Add Support for Rocktech RK043FN48H; plus DT bindings * Add support for Starry himax83102-j02; plus DT bindings * Add support for Starry ili9882t; plus DT bindings * virtio * Support sync-object UAPI Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230607085644.GA12673@linux-uq9g
This commit is contained in:
commit
45365b6588
32 changed files with 1989 additions and 221 deletions
1
.mailmap
1
.mailmap
|
@ -327,6 +327,7 @@ Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>
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|||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>
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Maxim Mikityanskiy <maxtram95@gmail.com> <maximmi@mellanox.com>
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Maxim Mikityanskiy <maxtram95@gmail.com> <maximmi@nvidia.com>
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Maxime Ripard <mripard@kernel.org> <maxime@cerno.tech>
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Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
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Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
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Mayuresh Janorkar <mayur@ti.com>
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|
|
|
@ -0,0 +1,118 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2020 BayLibre, SAS
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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description: |
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The Amlogic Meson Synopsys Designware Integration is composed of
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- A Synopsys DesignWare MIPI DSI Host Controller IP
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- A TOP control block controlling the Clocks & Resets of the IP
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allOf:
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- $ref: dsi-controller.yaml#
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properties:
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compatible:
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enum:
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- amlogic,meson-g12a-dw-mipi-dsi
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reg:
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maxItems: 1
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clocks:
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minItems: 3
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maxItems: 4
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clock-names:
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minItems: 3
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items:
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- const: pclk
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- const: bit
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- const: px
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- const: meas
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: top
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: dphy
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input node to receive pixel data.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: DSI output node to panel.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- phys
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- phy-names
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- ports
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unevaluatedProperties: false
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examples:
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- |
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dsi@6000 {
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compatible = "amlogic,meson-g12a-dw-mipi-dsi";
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reg = <0x6000 0x400>;
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resets = <&reset_top>;
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reset-names = "top";
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clocks = <&clk_pclk>, <&bit_clk>, <&clk_px>;
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clock-names = "pclk", "bit", "px";
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phys = <&mipi_dphy>;
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phy-names = "dphy";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* VPU VENC Input */
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mipi_dsi_venc_port: port@0 {
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reg = <0>;
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mipi_dsi_in: endpoint {
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remote-endpoint = <&dpi_out>;
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};
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};
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/* DSI Output */
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mipi_dsi_panel_port: port@1 {
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reg = <1>;
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mipi_out_panel: endpoint {
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remote-endpoint = <&mipi_in_panel>;
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};
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};
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};
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};
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|
@ -96,6 +96,11 @@ properties:
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description:
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A port node pointing to the HDMI-TX port node.
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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A port node pointing to the DPI port node (e.g. DSI or LVDS transceiver).
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"#address-cells":
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const: 1
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|
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@ -21,6 +21,9 @@ properties:
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maxItems: 1
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description: virtual channel number of a DSI peripheral
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reset-gpios:
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maxItems: 1
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vddc-supply:
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description: Regulator for 1.2V internal core power.
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|
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@ -32,6 +32,10 @@ properties:
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- innolux,hj110iz-01a
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# STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel
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- starry,2081101qfh032011-53g
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# STARRY himax83102-j02 10.51" WUXGA TFT LCD panel
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- starry,himax83102-j02
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# STARRY ili9882t 10.51" WUXGA TFT LCD panel
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- starry,ili9882t
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reg:
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description: the virtual channel number of a DSI peripheral
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|
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@ -286,6 +286,8 @@ properties:
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- rocktech,rk101ii01d-ct
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# Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel
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- rocktech,rk070er9427
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# Rocktech Display Ltd. RK043FN48H 4.3" 480x272 LCD-TFT panel
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- rocktech,rk043fn48h
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# Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
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- samsung,atna33xc20
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# Samsung 12.2" (2560x1600 pixels) TFT LCD panel
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|
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|
@ -17387,6 +17387,8 @@ F: include/dt-bindings/clock/qcom,*
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QUALCOMM CLOUD AI (QAIC) DRIVER
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M: Jeffrey Hugo <quic_jhugo@quicinc.com>
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R: Carl Vanderlip <quic_carlv@quicinc.com>
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R: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com>
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L: linux-arm-msm@vger.kernel.org
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L: dri-devel@lists.freedesktop.org
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S: Supported
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|
|
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@ -1,9 +1,13 @@
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if ARCH_MXC || COMPILE_TEST
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config DRM_IMX_LDB_HELPER
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tristate
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config DRM_IMX8QM_LDB
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tristate "Freescale i.MX8QM LVDS display bridge"
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depends on OF
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depends on COMMON_CLK
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select DRM_IMX_LDB_HELPER
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select DRM_KMS_HELPER
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help
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Choose this to enable the internal LVDS Display Bridge(LDB) found in
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@ -13,6 +17,7 @@ config DRM_IMX8QXP_LDB
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tristate "Freescale i.MX8QXP LVDS display bridge"
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depends on OF
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depends on COMMON_CLK
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select DRM_IMX_LDB_HELPER
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select DRM_KMS_HELPER
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help
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Choose this to enable the internal LVDS Display Bridge(LDB) found in
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|
|
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@ -1,9 +1,6 @@
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imx8qm-ldb-objs := imx-ldb-helper.o imx8qm-ldb-drv.o
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obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o
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obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
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imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o
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obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
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obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
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obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
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obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
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@ -4,8 +4,10 @@
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* Copyright 2019,2020,2022 NXP
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*/
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#include <linux/export.h>
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#include <linux/media-bus-format.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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@ -19,12 +21,14 @@ bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
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{
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return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
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}
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EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
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bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
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{
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return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
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ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
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}
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EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
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int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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@ -38,6 +42,7 @@ int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
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return 0;
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}
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EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
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void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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@ -69,6 +74,7 @@ void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
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break;
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}
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}
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EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
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void ldb_bridge_enable_helper(struct drm_bridge *bridge)
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{
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|
@ -81,6 +87,7 @@ void ldb_bridge_enable_helper(struct drm_bridge *bridge)
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*/
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regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
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}
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EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper);
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void ldb_bridge_disable_helper(struct drm_bridge *bridge)
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{
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|
@ -95,6 +102,7 @@ void ldb_bridge_disable_helper(struct drm_bridge *bridge)
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regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
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}
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EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper);
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int ldb_bridge_attach_helper(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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|
@ -117,6 +125,7 @@ int ldb_bridge_attach_helper(struct drm_bridge *bridge,
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ldb_ch->next_bridge, bridge,
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DRM_BRIDGE_ATTACH_NO_CONNECTOR);
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}
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EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper);
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int ldb_init_helper(struct ldb *ldb)
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{
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||||
|
@ -157,6 +166,7 @@ int ldb_init_helper(struct ldb *ldb)
|
|||
|
||||
return 0;
|
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}
|
||||
EXPORT_SYMBOL_GPL(ldb_init_helper);
|
||||
|
||||
int ldb_find_next_bridge_helper(struct ldb *ldb)
|
||||
{
|
||||
|
@ -184,6 +194,7 @@ int ldb_find_next_bridge_helper(struct ldb *ldb)
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper);
|
||||
|
||||
void ldb_add_bridge_helper(struct ldb *ldb,
|
||||
const struct drm_bridge_funcs *bridge_funcs)
|
||||
|
@ -204,6 +215,7 @@ void ldb_add_bridge_helper(struct ldb *ldb,
|
|||
drm_bridge_add(&ldb_ch->bridge);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ldb_add_bridge_helper);
|
||||
|
||||
void ldb_remove_bridge_helper(struct ldb *ldb)
|
||||
{
|
||||
|
@ -219,3 +231,8 @@ void ldb_remove_bridge_helper(struct ldb *ldb)
|
|||
drm_bridge_remove(&ldb_ch->bridge);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper);
|
||||
|
||||
MODULE_DESCRIPTION("i.MX8 LVDS Display Bridge(LDB)/Pixel Mapper bridge helper");
|
||||
MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_graph.h>
|
||||
|
@ -63,6 +64,7 @@ struct tc358762 {
|
|||
struct drm_bridge bridge;
|
||||
struct regulator *regulator;
|
||||
struct drm_bridge *panel_bridge;
|
||||
struct gpio_desc *reset_gpio;
|
||||
bool pre_enabled;
|
||||
int error;
|
||||
};
|
||||
|
@ -138,6 +140,9 @@ static void tc358762_post_disable(struct drm_bridge *bridge)
|
|||
|
||||
ctx->pre_enabled = false;
|
||||
|
||||
if (ctx->reset_gpio)
|
||||
gpiod_set_value_cansleep(ctx->reset_gpio, 0);
|
||||
|
||||
ret = regulator_disable(ctx->regulator);
|
||||
if (ret < 0)
|
||||
dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
|
||||
|
@ -152,6 +157,11 @@ static void tc358762_pre_enable(struct drm_bridge *bridge)
|
|||
if (ret < 0)
|
||||
dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
|
||||
|
||||
if (ctx->reset_gpio) {
|
||||
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
|
||||
usleep_range(5000, 10000);
|
||||
}
|
||||
|
||||
ret = tc358762_init(ctx);
|
||||
if (ret < 0)
|
||||
dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
|
||||
|
@ -185,6 +195,11 @@ static int tc358762_parse_dt(struct tc358762 *ctx)
|
|||
|
||||
ctx->panel_bridge = panel_bridge;
|
||||
|
||||
/* Reset GPIO is optional */
|
||||
ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
|
||||
if (IS_ERR(ctx->reset_gpio))
|
||||
return PTR_ERR(ctx->reset_gpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -17,3 +17,10 @@ config DRM_MESON_DW_HDMI
|
|||
default y if DRM_MESON
|
||||
select DRM_DW_HDMI
|
||||
imply DRM_DW_HDMI_I2S_AUDIO
|
||||
|
||||
config DRM_MESON_DW_MIPI_DSI
|
||||
tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
|
||||
depends on DRM_MESON
|
||||
default y if DRM_MESON
|
||||
select DRM_DW_MIPI_DSI
|
||||
select GENERIC_PHY_MIPI_DPHY
|
||||
|
|
|
@ -2,7 +2,8 @@
|
|||
meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_encoder_cvbs.o
|
||||
meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o
|
||||
meson-drm-y += meson_rdma.o meson_osd_afbcd.o
|
||||
meson-drm-y += meson_encoder_hdmi.o
|
||||
meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o
|
||||
|
||||
obj-$(CONFIG_DRM_MESON) += meson-drm.o
|
||||
obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
|
||||
obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#include "meson_registers.h"
|
||||
#include "meson_encoder_cvbs.h"
|
||||
#include "meson_encoder_hdmi.h"
|
||||
#include "meson_encoder_dsi.h"
|
||||
#include "meson_viu.h"
|
||||
#include "meson_vpp.h"
|
||||
#include "meson_rdma.h"
|
||||
|
@ -316,32 +317,40 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
|
|||
goto exit_afbcd;
|
||||
|
||||
if (has_components) {
|
||||
ret = component_bind_all(drm->dev, drm);
|
||||
ret = component_bind_all(dev, drm);
|
||||
if (ret) {
|
||||
dev_err(drm->dev, "Couldn't bind all components\n");
|
||||
/* Do not try to unbind */
|
||||
has_components = false;
|
||||
goto exit_afbcd;
|
||||
}
|
||||
}
|
||||
|
||||
ret = meson_encoder_hdmi_init(priv);
|
||||
if (ret)
|
||||
goto unbind_all;
|
||||
goto exit_afbcd;
|
||||
|
||||
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
|
||||
ret = meson_encoder_dsi_init(priv);
|
||||
if (ret)
|
||||
goto exit_afbcd;
|
||||
}
|
||||
|
||||
ret = meson_plane_create(priv);
|
||||
if (ret)
|
||||
goto unbind_all;
|
||||
goto exit_afbcd;
|
||||
|
||||
ret = meson_overlay_create(priv);
|
||||
if (ret)
|
||||
goto unbind_all;
|
||||
goto exit_afbcd;
|
||||
|
||||
ret = meson_crtc_create(priv);
|
||||
if (ret)
|
||||
goto unbind_all;
|
||||
goto exit_afbcd;
|
||||
|
||||
ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
|
||||
if (ret)
|
||||
goto unbind_all;
|
||||
goto exit_afbcd;
|
||||
|
||||
drm_mode_config_reset(drm);
|
||||
|
||||
|
@ -359,15 +368,19 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
|
|||
|
||||
uninstall_irq:
|
||||
free_irq(priv->vsync_irq, drm);
|
||||
unbind_all:
|
||||
if (has_components)
|
||||
component_unbind_all(drm->dev, drm);
|
||||
exit_afbcd:
|
||||
if (priv->afbcd.ops)
|
||||
priv->afbcd.ops->exit(priv);
|
||||
free_drm:
|
||||
drm_dev_put(drm);
|
||||
|
||||
meson_encoder_dsi_remove(priv);
|
||||
meson_encoder_hdmi_remove(priv);
|
||||
meson_encoder_cvbs_remove(priv);
|
||||
|
||||
if (has_components)
|
||||
component_unbind_all(dev, drm);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -394,6 +407,7 @@ static void meson_drv_unbind(struct device *dev)
|
|||
free_irq(priv->vsync_irq, drm);
|
||||
drm_dev_put(drm);
|
||||
|
||||
meson_encoder_dsi_remove(priv);
|
||||
meson_encoder_hdmi_remove(priv);
|
||||
meson_encoder_cvbs_remove(priv);
|
||||
|
||||
|
@ -446,10 +460,17 @@ static void meson_drv_shutdown(struct platform_device *pdev)
|
|||
drm_atomic_helper_shutdown(priv->drm);
|
||||
}
|
||||
|
||||
/* Possible connectors nodes to ignore */
|
||||
static const struct of_device_id connectors_match[] = {
|
||||
{ .compatible = "composite-video-connector" },
|
||||
{ .compatible = "svideo-connector" },
|
||||
/*
|
||||
* Only devices to use as components
|
||||
* TOFIX: get rid of components when we can finally
|
||||
* get meson_dx_hdmi to stop using the meson_drm
|
||||
* private structure for HHI registers.
|
||||
*/
|
||||
static const struct of_device_id components_dev_match[] = {
|
||||
{ .compatible = "amlogic,meson-gxbb-dw-hdmi" },
|
||||
{ .compatible = "amlogic,meson-gxl-dw-hdmi" },
|
||||
{ .compatible = "amlogic,meson-gxm-dw-hdmi" },
|
||||
{ .compatible = "amlogic,meson-g12a-dw-hdmi" },
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -467,18 +488,13 @@ static int meson_drv_probe(struct platform_device *pdev)
|
|||
continue;
|
||||
}
|
||||
|
||||
/* If an analog connector is detected, count it as an output */
|
||||
if (of_match_node(connectors_match, remote)) {
|
||||
++count;
|
||||
of_node_put(remote);
|
||||
continue;
|
||||
if (of_match_node(components_dev_match, remote)) {
|
||||
component_match_add(&pdev->dev, &match, component_compare_of, remote);
|
||||
|
||||
dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n",
|
||||
np, remote, dev_name(&pdev->dev));
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n",
|
||||
np, remote, dev_name(&pdev->dev));
|
||||
|
||||
component_match_add(&pdev->dev, &match, component_compare_of, remote);
|
||||
|
||||
of_node_put(remote);
|
||||
|
||||
++count;
|
||||
|
|
|
@ -28,6 +28,7 @@ enum vpu_compatible {
|
|||
enum {
|
||||
MESON_ENC_CVBS = 0,
|
||||
MESON_ENC_HDMI,
|
||||
MESON_ENC_DSI,
|
||||
MESON_ENC_LAST,
|
||||
};
|
||||
|
||||
|
|
352
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
Normal file
352
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
Normal file
|
@ -0,0 +1,352 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2021 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_graph.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#include <video/mipi_display.h>
|
||||
|
||||
#include <drm/bridge/dw_mipi_dsi.h>
|
||||
#include <drm/drm_mipi_dsi.h>
|
||||
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_device.h>
|
||||
#include <drm/drm_probe_helper.h>
|
||||
#include <drm/drm_print.h>
|
||||
|
||||
#include "meson_drv.h"
|
||||
#include "meson_dw_mipi_dsi.h"
|
||||
#include "meson_registers.h"
|
||||
#include "meson_venc.h"
|
||||
|
||||
#define DRIVER_NAME "meson-dw-mipi-dsi"
|
||||
#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
|
||||
|
||||
struct meson_dw_mipi_dsi {
|
||||
struct meson_drm *priv;
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct phy *phy;
|
||||
union phy_configure_opts phy_opts;
|
||||
struct dw_mipi_dsi *dmd;
|
||||
struct dw_mipi_dsi_plat_data pdata;
|
||||
struct mipi_dsi_device *dsi_device;
|
||||
const struct drm_display_mode *mode;
|
||||
struct clk *bit_clk;
|
||||
struct clk *px_clk;
|
||||
struct reset_control *top_rst;
|
||||
};
|
||||
|
||||
#define encoder_to_meson_dw_mipi_dsi(x) \
|
||||
container_of(x, struct meson_dw_mipi_dsi, encoder)
|
||||
|
||||
static void meson_dw_mipi_dsi_hw_init(struct meson_dw_mipi_dsi *mipi_dsi)
|
||||
{
|
||||
/* Software reset */
|
||||
writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
|
||||
MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING,
|
||||
MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
|
||||
MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING,
|
||||
mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
|
||||
writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR |
|
||||
MIPI_DSI_TOP_SW_RESET_DPI | MIPI_DSI_TOP_SW_RESET_TIMING,
|
||||
0, mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
|
||||
|
||||
/* Enable clocks */
|
||||
writel_bits_relaxed(MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN,
|
||||
MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN,
|
||||
mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
|
||||
|
||||
/* Take memory out of power down */
|
||||
writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
|
||||
}
|
||||
|
||||
static int dw_mipi_dsi_phy_init(void *priv_data)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
|
||||
unsigned int dpi_data_format, venc_data_width;
|
||||
int ret;
|
||||
|
||||
/* Set the bit clock rate to hs_clk_rate */
|
||||
ret = clk_set_rate(mipi_dsi->bit_clk,
|
||||
mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
|
||||
if (ret) {
|
||||
dev_err(mipi_dsi->dev, "Failed to set DSI Bit clock rate %lu (ret %d)\n",
|
||||
mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Make sure the rate of the bit clock is not modified by someone else */
|
||||
ret = clk_rate_exclusive_get(mipi_dsi->bit_clk);
|
||||
if (ret) {
|
||||
dev_err(mipi_dsi->dev,
|
||||
"Failed to set the exclusivity on the bit clock rate (ret %d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000);
|
||||
|
||||
if (ret) {
|
||||
dev_err(mipi_dsi->dev, "Failed to set DSI Pixel clock rate %u (%d)\n",
|
||||
mipi_dsi->mode->clock * 1000, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (mipi_dsi->dsi_device->format) {
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
dpi_data_format = DPI_COLOR_24BIT;
|
||||
venc_data_width = VENC_IN_COLOR_24B;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666:
|
||||
dpi_data_format = DPI_COLOR_18BIT_CFG_2;
|
||||
venc_data_width = VENC_IN_COLOR_18B;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Configure color format for DPI register */
|
||||
writel_relaxed(FIELD_PREP(MIPI_DSI_TOP_DPI_COLOR_MODE, dpi_data_format) |
|
||||
FIELD_PREP(MIPI_DSI_TOP_IN_COLOR_MODE, venc_data_width) |
|
||||
FIELD_PREP(MIPI_DSI_TOP_COMP2_SEL, 2) |
|
||||
FIELD_PREP(MIPI_DSI_TOP_COMP1_SEL, 1) |
|
||||
FIELD_PREP(MIPI_DSI_TOP_COMP0_SEL, 0),
|
||||
mipi_dsi->base + MIPI_DSI_TOP_CNTL);
|
||||
|
||||
return phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
|
||||
}
|
||||
|
||||
static void dw_mipi_dsi_phy_power_on(void *priv_data)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
|
||||
|
||||
if (phy_power_on(mipi_dsi->phy))
|
||||
dev_warn(mipi_dsi->dev, "Failed to power on PHY\n");
|
||||
}
|
||||
|
||||
static void dw_mipi_dsi_phy_power_off(void *priv_data)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
|
||||
|
||||
if (phy_power_off(mipi_dsi->phy))
|
||||
dev_warn(mipi_dsi->dev, "Failed to power off PHY\n");
|
||||
|
||||
/* Remove the exclusivity on the bit clock rate */
|
||||
clk_rate_exclusive_put(mipi_dsi->bit_clk);
|
||||
}
|
||||
|
||||
static int
|
||||
dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
|
||||
unsigned long mode_flags, u32 lanes, u32 format,
|
||||
unsigned int *lane_mbps)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
|
||||
int bpp;
|
||||
|
||||
mipi_dsi->mode = mode;
|
||||
|
||||
bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
|
||||
|
||||
phy_mipi_dphy_get_default_config(mode->clock * 1000,
|
||||
bpp, mipi_dsi->dsi_device->lanes,
|
||||
&mipi_dsi->phy_opts.mipi_dphy);
|
||||
|
||||
*lane_mbps = DIV_ROUND_UP(mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, USEC_PER_SEC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
|
||||
struct dw_mipi_dsi_dphy_timing *timing)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
|
||||
|
||||
switch (mipi_dsi->mode->hdisplay) {
|
||||
case 240:
|
||||
case 768:
|
||||
case 1920:
|
||||
case 2560:
|
||||
timing->clk_lp2hs = 23;
|
||||
timing->clk_hs2lp = 38;
|
||||
timing->data_lp2hs = 15;
|
||||
timing->data_hs2lp = 9;
|
||||
break;
|
||||
|
||||
default:
|
||||
timing->clk_lp2hs = 37;
|
||||
timing->clk_hs2lp = 135;
|
||||
timing->data_lp2hs = 50;
|
||||
timing->data_hs2lp = 3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
|
||||
{
|
||||
*esc_clk_rate = 4; /* Mhz */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
|
||||
.init = dw_mipi_dsi_phy_init,
|
||||
.power_on = dw_mipi_dsi_phy_power_on,
|
||||
.power_off = dw_mipi_dsi_phy_power_off,
|
||||
.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
|
||||
.get_timing = dw_mipi_dsi_phy_get_timing,
|
||||
.get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
|
||||
};
|
||||
|
||||
static int meson_dw_mipi_dsi_host_attach(void *priv_data,
|
||||
struct mipi_dsi_device *device)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
|
||||
int ret;
|
||||
|
||||
mipi_dsi->dsi_device = device;
|
||||
|
||||
switch (device->format) {
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666:
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
dev_err(mipi_dsi->dev, "invalid pixel format %d\n", device->format);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = phy_init(mipi_dsi->phy);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_dw_mipi_dsi_hw_init(mipi_dsi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_dw_mipi_dsi_host_detach(void *priv_data,
|
||||
struct mipi_dsi_device *device)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
|
||||
|
||||
if (device == mipi_dsi->dsi_device)
|
||||
mipi_dsi->dsi_device = NULL;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
return phy_exit(mipi_dsi->phy);
|
||||
}
|
||||
|
||||
static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
|
||||
.attach = meson_dw_mipi_dsi_host_attach,
|
||||
.detach = meson_dw_mipi_dsi_host_detach,
|
||||
};
|
||||
|
||||
static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
mipi_dsi = devm_kzalloc(dev, sizeof(*mipi_dsi), GFP_KERNEL);
|
||||
if (!mipi_dsi)
|
||||
return -ENOMEM;
|
||||
|
||||
mipi_dsi->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(mipi_dsi->base))
|
||||
return PTR_ERR(mipi_dsi->base);
|
||||
|
||||
mipi_dsi->phy = devm_phy_get(dev, "dphy");
|
||||
if (IS_ERR(mipi_dsi->phy))
|
||||
return dev_err_probe(dev, PTR_ERR(mipi_dsi->phy),
|
||||
"failed to get mipi dphy\n");
|
||||
|
||||
mipi_dsi->bit_clk = devm_clk_get_enabled(dev, "bit");
|
||||
if (IS_ERR(mipi_dsi->bit_clk)) {
|
||||
int ret = PTR_ERR(mipi_dsi->bit_clk);
|
||||
|
||||
/* TOFIX GP0 on some platforms fails to lock in early boot, defer probe */
|
||||
if (ret == -EIO)
|
||||
ret = -EPROBE_DEFER;
|
||||
|
||||
return dev_err_probe(dev, ret, "Unable to get enabled bit_clk\n");
|
||||
}
|
||||
|
||||
mipi_dsi->px_clk = devm_clk_get_enabled(dev, "px");
|
||||
if (IS_ERR(mipi_dsi->px_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(mipi_dsi->px_clk),
|
||||
"Unable to get enabled px_clk\n");
|
||||
|
||||
/*
|
||||
* We use a TOP reset signal because the APB reset signal
|
||||
* is handled by the TOP control registers.
|
||||
*/
|
||||
mipi_dsi->top_rst = devm_reset_control_get_exclusive(dev, "top");
|
||||
if (IS_ERR(mipi_dsi->top_rst))
|
||||
return dev_err_probe(dev, PTR_ERR(mipi_dsi->top_rst),
|
||||
"Unable to get reset control\n");
|
||||
|
||||
reset_control_assert(mipi_dsi->top_rst);
|
||||
usleep_range(10, 20);
|
||||
reset_control_deassert(mipi_dsi->top_rst);
|
||||
|
||||
/* MIPI DSI Controller */
|
||||
|
||||
mipi_dsi->dev = dev;
|
||||
mipi_dsi->pdata.base = mipi_dsi->base;
|
||||
mipi_dsi->pdata.max_data_lanes = 4;
|
||||
mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
|
||||
mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
|
||||
mipi_dsi->pdata.priv_data = mipi_dsi;
|
||||
platform_set_drvdata(pdev, mipi_dsi);
|
||||
|
||||
mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
|
||||
if (IS_ERR(mipi_dsi->dmd))
|
||||
return dev_err_probe(dev, PTR_ERR(mipi_dsi->dmd),
|
||||
"Failed to probe dw_mipi_dsi\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct meson_dw_mipi_dsi *mipi_dsi = platform_get_drvdata(pdev);
|
||||
|
||||
dw_mipi_dsi_remove(mipi_dsi->dmd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
|
||||
{ .compatible = "amlogic,meson-g12a-dw-mipi-dsi", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
|
||||
|
||||
static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
|
||||
.probe = meson_dw_mipi_dsi_probe,
|
||||
.remove = meson_dw_mipi_dsi_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = meson_dw_mipi_dsi_of_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(meson_dw_mipi_dsi_platform_driver);
|
||||
|
||||
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
||||
MODULE_DESCRIPTION(DRIVER_DESC);
|
||||
MODULE_LICENSE("GPL");
|
160
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h
Normal file
160
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h
Normal file
|
@ -0,0 +1,160 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2020 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __MESON_DW_MIPI_DSI_H
|
||||
#define __MESON_DW_MIPI_DSI_H
|
||||
|
||||
/* Top-level registers */
|
||||
/* [31: 4] Reserved. Default 0.
|
||||
* [3] RW timing_rst_n: Default 1.
|
||||
* 1=Assert SW reset of timing feature. 0=Release reset.
|
||||
* [2] RW dpi_rst_n: Default 1.
|
||||
* 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset.
|
||||
* [1] RW intr_rst_n: Default 1.
|
||||
* 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset.
|
||||
* [0] RW dwc_rst_n: Default 1.
|
||||
* 1=Assert SW reset on IP core. 0=Release reset.
|
||||
*/
|
||||
#define MIPI_DSI_TOP_SW_RESET 0x3c0
|
||||
|
||||
#define MIPI_DSI_TOP_SW_RESET_DWC BIT(0)
|
||||
#define MIPI_DSI_TOP_SW_RESET_INTR BIT(1)
|
||||
#define MIPI_DSI_TOP_SW_RESET_DPI BIT(2)
|
||||
#define MIPI_DSI_TOP_SW_RESET_TIMING BIT(3)
|
||||
|
||||
/* [31: 5] Reserved. Default 0.
|
||||
* [4] RW manual_edpihalt: Default 0.
|
||||
* 1=Manual suspend VencL; 0=do not suspend VencL.
|
||||
* [3] RW auto_edpihalt_en: Default 0.
|
||||
* 1=Enable IP's edpihalt signal to suspend VencL;
|
||||
* 0=IP's edpihalt signal does not affect VencL.
|
||||
* [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
|
||||
* 0=Default, use auto-clock gating to save power;
|
||||
* 1=use free-run clock, disable auto-clock gating, for debug mode.
|
||||
* [1] RW enable_pixclk: A manual clock gate option, due to DWC IP does not
|
||||
* have auto-clock gating. 1=Enable pixclk. Default 0.
|
||||
* [0] RW enable_sysclk: A manual clock gate option, due to DWC IP does not
|
||||
* have auto-clock gating. 1=Enable sysclk. Default 0.
|
||||
*/
|
||||
#define MIPI_DSI_TOP_CLK_CNTL 0x3c4
|
||||
|
||||
#define MIPI_DSI_TOP_CLK_SYSCLK_EN BIT(0)
|
||||
#define MIPI_DSI_TOP_CLK_PIXCLK_EN BIT(1)
|
||||
|
||||
/* [31:24] Reserved. Default 0.
|
||||
* [23:20] RW dpi_color_mode: Define DPI pixel format. Default 0.
|
||||
* 0=16-bit RGB565 config 1;
|
||||
* 1=16-bit RGB565 config 2;
|
||||
* 2=16-bit RGB565 config 3;
|
||||
* 3=18-bit RGB666 config 1;
|
||||
* 4=18-bit RGB666 config 2;
|
||||
* 5=24-bit RGB888;
|
||||
* 6=20-bit YCbCr 4:2:2;
|
||||
* 7=24-bit YCbCr 4:2:2;
|
||||
* 8=16-bit YCbCr 4:2:2;
|
||||
* 9=30-bit RGB;
|
||||
* 10=36-bit RGB;
|
||||
* 11=12-bit YCbCr 4:2:0.
|
||||
* [19] Reserved. Default 0.
|
||||
* [18:16] RW in_color_mode: Define VENC data width. Default 0.
|
||||
* 0=30-bit pixel;
|
||||
* 1=24-bit pixel;
|
||||
* 2=18-bit pixel, RGB666;
|
||||
* 3=16-bit pixel, RGB565.
|
||||
* [15:14] RW chroma_subsample: Define method of chroma subsampling. Default 0.
|
||||
* Applicable to YUV422 or YUV420 only.
|
||||
* 0=Use even pixel's chroma;
|
||||
* 1=Use odd pixel's chroma;
|
||||
* 2=Use averaged value between even and odd pair.
|
||||
* [13:12] RW comp2_sel: Select which component to be Cr or B: Default 2.
|
||||
* 0=comp0; 1=comp1; 2=comp2.
|
||||
* [11:10] RW comp1_sel: Select which component to be Cb or G: Default 1.
|
||||
* 0=comp0; 1=comp1; 2=comp2.
|
||||
* [9: 8] RW comp0_sel: Select which component to be Y or R: Default 0.
|
||||
* 0=comp0; 1=comp1; 2=comp2.
|
||||
* [7] Reserved. Default 0.
|
||||
* [6] RW de_pol: Default 0.
|
||||
* If DE input is active low, set to 1 to invert to active high.
|
||||
* [5] RW hsync_pol: Default 0.
|
||||
* If HS input is active low, set to 1 to invert to active high.
|
||||
* [4] RW vsync_pol: Default 0.
|
||||
* If VS input is active low, set to 1 to invert to active high.
|
||||
* [3] RW dpicolorm: Signal to IP. Default 0.
|
||||
* [2] RW dpishutdn: Signal to IP. Default 0.
|
||||
* [1] Reserved. Default 0.
|
||||
* [0] Reserved. Default 0.
|
||||
*/
|
||||
#define MIPI_DSI_TOP_CNTL 0x3c8
|
||||
|
||||
/* VENC data width */
|
||||
#define VENC_IN_COLOR_30B 0x0
|
||||
#define VENC_IN_COLOR_24B 0x1
|
||||
#define VENC_IN_COLOR_18B 0x2
|
||||
#define VENC_IN_COLOR_16B 0x3
|
||||
|
||||
/* DPI pixel format */
|
||||
#define DPI_COLOR_16BIT_CFG_1 0
|
||||
#define DPI_COLOR_16BIT_CFG_2 1
|
||||
#define DPI_COLOR_16BIT_CFG_3 2
|
||||
#define DPI_COLOR_18BIT_CFG_1 3
|
||||
#define DPI_COLOR_18BIT_CFG_2 4
|
||||
#define DPI_COLOR_24BIT 5
|
||||
#define DPI_COLOR_20BIT_YCBCR_422 6
|
||||
#define DPI_COLOR_24BIT_YCBCR_422 7
|
||||
#define DPI_COLOR_16BIT_YCBCR_422 8
|
||||
#define DPI_COLOR_30BIT 9
|
||||
#define DPI_COLOR_36BIT 10
|
||||
#define DPI_COLOR_12BIT_YCBCR_420 11
|
||||
|
||||
#define MIPI_DSI_TOP_DPI_COLOR_MODE GENMASK(23, 20)
|
||||
#define MIPI_DSI_TOP_IN_COLOR_MODE GENMASK(18, 16)
|
||||
#define MIPI_DSI_TOP_CHROMA_SUBSAMPLE GENMASK(15, 14)
|
||||
#define MIPI_DSI_TOP_COMP2_SEL GENMASK(13, 12)
|
||||
#define MIPI_DSI_TOP_COMP1_SEL GENMASK(11, 10)
|
||||
#define MIPI_DSI_TOP_COMP0_SEL GENMASK(9, 8)
|
||||
#define MIPI_DSI_TOP_DE_INVERT BIT(6)
|
||||
#define MIPI_DSI_TOP_HSYNC_INVERT BIT(5)
|
||||
#define MIPI_DSI_TOP_VSYNC_INVERT BIT(4)
|
||||
#define MIPI_DSI_TOP_DPICOLORM BIT(3)
|
||||
#define MIPI_DSI_TOP_DPISHUTDN BIT(2)
|
||||
|
||||
#define MIPI_DSI_TOP_SUSPEND_CNTL 0x3cc
|
||||
#define MIPI_DSI_TOP_SUSPEND_LINE 0x3d0
|
||||
#define MIPI_DSI_TOP_SUSPEND_PIX 0x3d4
|
||||
#define MIPI_DSI_TOP_MEAS_CNTL 0x3d8
|
||||
/* [0] R stat_edpihalt: edpihalt signal from IP. Default 0. */
|
||||
#define MIPI_DSI_TOP_STAT 0x3dc
|
||||
#define MIPI_DSI_TOP_MEAS_STAT_TE0 0x3e0
|
||||
#define MIPI_DSI_TOP_MEAS_STAT_TE1 0x3e4
|
||||
#define MIPI_DSI_TOP_MEAS_STAT_VS0 0x3e8
|
||||
#define MIPI_DSI_TOP_MEAS_STAT_VS1 0x3ec
|
||||
/* [31:16] RW intr_stat/clr. Default 0.
|
||||
* For each bit, read as this interrupt level status,
|
||||
* write 1 to clear.
|
||||
* [31:22] Reserved
|
||||
* [ 21] stat/clr of eof interrupt
|
||||
* [ 21] vde_fall interrupt
|
||||
* [ 19] stat/clr of de_rise interrupt
|
||||
* [ 18] stat/clr of vs_fall interrupt
|
||||
* [ 17] stat/clr of vs_rise interrupt
|
||||
* [ 16] stat/clr of dwc_edpite interrupt
|
||||
* [15: 0] RW intr_enable. Default 0.
|
||||
* For each bit, 1=enable this interrupt, 0=disable.
|
||||
* [15: 6] Reserved
|
||||
* [ 5] eof interrupt
|
||||
* [ 4] de_fall interrupt
|
||||
* [ 3] de_rise interrupt
|
||||
* [ 2] vs_fall interrupt
|
||||
* [ 1] vs_rise interrupt
|
||||
* [ 0] dwc_edpite interrupt
|
||||
*/
|
||||
#define MIPI_DSI_TOP_INTR_CNTL_STAT 0x3f0
|
||||
// 31: 2 Reserved. Default 0.
|
||||
// 1: 0 RW mem_pd. Default 3.
|
||||
#define MIPI_DSI_TOP_MEM_PD 0x3f4
|
||||
|
||||
#endif /* __MESON_DW_MIPI_DSI_H */
|
174
drivers/gpu/drm/meson/meson_encoder_dsi.c
Normal file
174
drivers/gpu/drm/meson/meson_encoder_dsi.c
Normal file
|
@ -0,0 +1,174 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_graph.h>
|
||||
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_simple_kms_helper.h>
|
||||
#include <drm/drm_bridge.h>
|
||||
#include <drm/drm_bridge_connector.h>
|
||||
#include <drm/drm_device.h>
|
||||
#include <drm/drm_probe_helper.h>
|
||||
|
||||
#include "meson_drv.h"
|
||||
#include "meson_encoder_dsi.h"
|
||||
#include "meson_registers.h"
|
||||
#include "meson_venc.h"
|
||||
#include "meson_vclk.h"
|
||||
|
||||
struct meson_encoder_dsi {
|
||||
struct drm_encoder encoder;
|
||||
struct drm_bridge bridge;
|
||||
struct drm_bridge *next_bridge;
|
||||
struct meson_drm *priv;
|
||||
};
|
||||
|
||||
#define bridge_to_meson_encoder_dsi(x) \
|
||||
container_of(x, struct meson_encoder_dsi, bridge)
|
||||
|
||||
static int meson_encoder_dsi_attach(struct drm_bridge *bridge,
|
||||
enum drm_bridge_attach_flags flags)
|
||||
{
|
||||
struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge);
|
||||
|
||||
return drm_bridge_attach(bridge->encoder, encoder_dsi->next_bridge,
|
||||
&encoder_dsi->bridge, flags);
|
||||
}
|
||||
|
||||
static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *bridge_state)
|
||||
{
|
||||
struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge);
|
||||
struct drm_atomic_state *state = bridge_state->base.state;
|
||||
struct meson_drm *priv = encoder_dsi->priv;
|
||||
struct drm_connector_state *conn_state;
|
||||
struct drm_crtc_state *crtc_state;
|
||||
struct drm_connector *connector;
|
||||
|
||||
connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
|
||||
if (WARN_ON(!connector))
|
||||
return;
|
||||
|
||||
conn_state = drm_atomic_get_new_connector_state(state, connector);
|
||||
if (WARN_ON(!conn_state))
|
||||
return;
|
||||
|
||||
crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
|
||||
if (WARN_ON(!crtc_state))
|
||||
return;
|
||||
|
||||
/* ENCL clock setup is handled by CCF */
|
||||
|
||||
meson_venc_mipi_dsi_mode_set(priv, &crtc_state->adjusted_mode);
|
||||
meson_encl_load_gamma(priv);
|
||||
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
|
||||
|
||||
writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, ENCL_VIDEO_MODE_ADV_VFIFO_EN,
|
||||
priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
|
||||
|
||||
writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
|
||||
|
||||
writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
|
||||
}
|
||||
|
||||
static void meson_encoder_dsi_atomic_disable(struct drm_bridge *bridge,
|
||||
struct drm_bridge_state *bridge_state)
|
||||
{
|
||||
struct meson_encoder_dsi *meson_encoder_dsi =
|
||||
bridge_to_meson_encoder_dsi(bridge);
|
||||
struct meson_drm *priv = meson_encoder_dsi->priv;
|
||||
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
|
||||
|
||||
writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
|
||||
}
|
||||
|
||||
static const struct drm_bridge_funcs meson_encoder_dsi_bridge_funcs = {
|
||||
.attach = meson_encoder_dsi_attach,
|
||||
.atomic_enable = meson_encoder_dsi_atomic_enable,
|
||||
.atomic_disable = meson_encoder_dsi_atomic_disable,
|
||||
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
|
||||
.atomic_reset = drm_atomic_helper_bridge_reset,
|
||||
};
|
||||
|
||||
int meson_encoder_dsi_init(struct meson_drm *priv)
|
||||
{
|
||||
struct meson_encoder_dsi *meson_encoder_dsi;
|
||||
struct device_node *remote;
|
||||
int ret;
|
||||
|
||||
meson_encoder_dsi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_dsi), GFP_KERNEL);
|
||||
if (!meson_encoder_dsi)
|
||||
return -ENOMEM;
|
||||
|
||||
/* DSI Transceiver Bridge */
|
||||
remote = of_graph_get_remote_node(priv->dev->of_node, 2, 0);
|
||||
if (!remote) {
|
||||
dev_err(priv->dev, "DSI transceiver device is disabled");
|
||||
return 0;
|
||||
}
|
||||
|
||||
meson_encoder_dsi->next_bridge = of_drm_find_bridge(remote);
|
||||
if (!meson_encoder_dsi->next_bridge) {
|
||||
dev_dbg(priv->dev, "Failed to find DSI transceiver bridge\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
/* DSI Encoder Bridge */
|
||||
meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs;
|
||||
meson_encoder_dsi->bridge.of_node = priv->dev->of_node;
|
||||
meson_encoder_dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
|
||||
|
||||
drm_bridge_add(&meson_encoder_dsi->bridge);
|
||||
|
||||
meson_encoder_dsi->priv = priv;
|
||||
|
||||
/* Encoder */
|
||||
ret = drm_simple_encoder_init(priv->drm, &meson_encoder_dsi->encoder,
|
||||
DRM_MODE_ENCODER_DSI);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "Failed to init DSI encoder: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
meson_encoder_dsi->encoder.possible_crtcs = BIT(0);
|
||||
|
||||
/* Attach DSI Encoder Bridge to Encoder */
|
||||
ret = drm_bridge_attach(&meson_encoder_dsi->encoder, &meson_encoder_dsi->bridge, NULL, 0);
|
||||
if (ret) {
|
||||
dev_err(priv->dev, "Failed to attach bridge: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* We should have now in place:
|
||||
* encoder->[dsi encoder bridge]->[dw-mipi-dsi bridge]->[panel bridge]->[panel]
|
||||
*/
|
||||
|
||||
priv->encoders[MESON_ENC_DSI] = meson_encoder_dsi;
|
||||
|
||||
dev_dbg(priv->dev, "DSI encoder initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void meson_encoder_dsi_remove(struct meson_drm *priv)
|
||||
{
|
||||
struct meson_encoder_dsi *meson_encoder_dsi;
|
||||
|
||||
if (priv->encoders[MESON_ENC_DSI]) {
|
||||
meson_encoder_dsi = priv->encoders[MESON_ENC_DSI];
|
||||
drm_bridge_remove(&meson_encoder_dsi->bridge);
|
||||
drm_bridge_remove(meson_encoder_dsi->next_bridge);
|
||||
}
|
||||
}
|
13
drivers/gpu/drm/meson/meson_encoder_dsi.h
Normal file
13
drivers/gpu/drm/meson/meson_encoder_dsi.h
Normal file
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2021 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __MESON_ENCODER_DSI_H
|
||||
#define __MESON_ENCODER_DSI_H
|
||||
|
||||
int meson_encoder_dsi_init(struct meson_drm *priv);
|
||||
void meson_encoder_dsi_remove(struct meson_drm *priv);
|
||||
|
||||
#endif /* __MESON_ENCODER_DSI_H */
|
|
@ -812,6 +812,7 @@
|
|||
#define VENC_STATA 0x1b6d
|
||||
#define VENC_INTCTRL 0x1b6e
|
||||
#define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1)
|
||||
#define VENC_INTCTRL_ENCP_LNRST_INT_EN BIT(9)
|
||||
#define VENC_INTFLAG 0x1b6f
|
||||
#define VENC_VIDEO_TST_EN 0x1b70
|
||||
#define VENC_VIDEO_TST_MDSEL 0x1b71
|
||||
|
@ -1192,7 +1193,11 @@
|
|||
#define ENCL_VIDEO_PB_OFFST 0x1ca5
|
||||
#define ENCL_VIDEO_PR_OFFST 0x1ca6
|
||||
#define ENCL_VIDEO_MODE 0x1ca7
|
||||
#define ENCL_PX_LN_CNT_SHADOW_EN BIT(15)
|
||||
#define ENCL_VIDEO_MODE_ADV 0x1ca8
|
||||
#define ENCL_VIDEO_MODE_ADV_VFIFO_EN BIT(3)
|
||||
#define ENCL_VIDEO_MODE_ADV_GAIN_HDTV BIT(4)
|
||||
#define ENCL_SEL_GAMMA_RGB_IN BIT(10)
|
||||
#define ENCL_DBG_PX_RST 0x1ca9
|
||||
#define ENCL_DBG_LN_RST 0x1caa
|
||||
#define ENCL_DBG_PX_INT 0x1cab
|
||||
|
@ -1219,11 +1224,14 @@
|
|||
#define ENCL_VIDEO_VOFFST 0x1cc0
|
||||
#define ENCL_VIDEO_RGB_CTRL 0x1cc1
|
||||
#define ENCL_VIDEO_FILT_CTRL 0x1cc2
|
||||
#define ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER BIT(12)
|
||||
#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3
|
||||
#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4
|
||||
#define ENCL_VIDEO_MATRIX_CB 0x1cc5
|
||||
#define ENCL_VIDEO_MATRIX_CR 0x1cc6
|
||||
#define ENCL_VIDEO_RGBIN_CTRL 0x1cc7
|
||||
#define ENCL_VIDEO_RGBIN_RGB BIT(0)
|
||||
#define ENCL_VIDEO_RGBIN_ZBLK BIT(1)
|
||||
#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8
|
||||
#define ENCL_DACSEL_0 0x1cc9
|
||||
#define ENCL_DACSEL_1 0x1cca
|
||||
|
@ -1300,13 +1308,28 @@
|
|||
#define RDMA_STATUS2 0x1116
|
||||
#define RDMA_STATUS3 0x1117
|
||||
#define L_GAMMA_CNTL_PORT 0x1400
|
||||
#define L_GAMMA_CNTL_PORT_VCOM_POL BIT(7) /* RW */
|
||||
#define L_GAMMA_CNTL_PORT_RVS_OUT BIT(6) /* RW */
|
||||
#define L_GAMMA_CNTL_PORT_ADR_RDY BIT(5) /* Read Only */
|
||||
#define L_GAMMA_CNTL_PORT_WR_RDY BIT(4) /* Read Only */
|
||||
#define L_GAMMA_CNTL_PORT_RD_RDY BIT(3) /* Read Only */
|
||||
#define L_GAMMA_CNTL_PORT_TR BIT(2) /* RW */
|
||||
#define L_GAMMA_CNTL_PORT_SET BIT(1) /* RW */
|
||||
#define L_GAMMA_CNTL_PORT_EN BIT(0) /* RW */
|
||||
#define L_GAMMA_DATA_PORT 0x1401
|
||||
#define L_GAMMA_ADDR_PORT 0x1402
|
||||
#define L_GAMMA_ADDR_PORT_RD BIT(12)
|
||||
#define L_GAMMA_ADDR_PORT_AUTO_INC BIT(11)
|
||||
#define L_GAMMA_ADDR_PORT_SEL_R BIT(10)
|
||||
#define L_GAMMA_ADDR_PORT_SEL_G BIT(9)
|
||||
#define L_GAMMA_ADDR_PORT_SEL_B BIT(8)
|
||||
#define L_GAMMA_ADDR_PORT_ADDR GENMASK(7, 0)
|
||||
#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403
|
||||
#define L_RGB_BASE_ADDR 0x1405
|
||||
#define L_RGB_COEFF_ADDR 0x1406
|
||||
#define L_POL_CNTL_ADDR 0x1407
|
||||
#define L_DITH_CNTL_ADDR 0x1408
|
||||
#define L_DITH_CNTL_DITH10_EN BIT(10)
|
||||
#define L_GAMMA_PROBE_CTRL 0x1409
|
||||
#define L_GAMMA_PROBE_COLOR_L 0x140a
|
||||
#define L_GAMMA_PROBE_COLOR_H 0x140b
|
||||
|
@ -1363,6 +1386,8 @@
|
|||
#define L_LCD_PWM1_HI_ADDR 0x143f
|
||||
#define L_INV_CNT_ADDR 0x1440
|
||||
#define L_TCON_MISC_SEL_ADDR 0x1441
|
||||
#define L_TCON_MISC_SEL_STV1 BIT(4)
|
||||
#define L_TCON_MISC_SEL_STV2 BIT(5)
|
||||
#define L_DUAL_PORT_CNTL_ADDR 0x1442
|
||||
#define MLVDS_CLK_CTL1_HI 0x1443
|
||||
#define MLVDS_CLK_CTL1_LO 0x1444
|
||||
|
|
|
@ -5,7 +5,9 @@
|
|||
* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
#include <drm/drm_modes.h>
|
||||
|
||||
|
@ -1557,6 +1559,205 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
|
||||
|
||||
static unsigned short meson_encl_gamma_table[256] = {
|
||||
0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
|
||||
64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124,
|
||||
128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188,
|
||||
192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252,
|
||||
256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316,
|
||||
320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380,
|
||||
384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444,
|
||||
448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508,
|
||||
512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572,
|
||||
576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636,
|
||||
640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700,
|
||||
704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764,
|
||||
768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828,
|
||||
832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892,
|
||||
896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956,
|
||||
960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020,
|
||||
};
|
||||
|
||||
static void meson_encl_set_gamma_table(struct meson_drm *priv, u16 *data,
|
||||
u32 rgb_mask)
|
||||
{
|
||||
int i, ret;
|
||||
u32 reg;
|
||||
|
||||
writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, 0,
|
||||
priv->io_base + _REG(L_GAMMA_CNTL_PORT));
|
||||
|
||||
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
|
||||
reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000);
|
||||
if (ret)
|
||||
pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__);
|
||||
|
||||
writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask |
|
||||
FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0),
|
||||
priv->io_base + _REG(L_GAMMA_ADDR_PORT));
|
||||
|
||||
for (i = 0; i < 256; i++) {
|
||||
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
|
||||
reg, reg & L_GAMMA_CNTL_PORT_WR_RDY,
|
||||
10, 10000);
|
||||
if (ret)
|
||||
pr_warn_once("%s: GAMMA WR_RDY timeout\n", __func__);
|
||||
|
||||
writel_relaxed(data[i], priv->io_base + _REG(L_GAMMA_DATA_PORT));
|
||||
}
|
||||
|
||||
ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT),
|
||||
reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000);
|
||||
if (ret)
|
||||
pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__);
|
||||
|
||||
writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask |
|
||||
FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0x23),
|
||||
priv->io_base + _REG(L_GAMMA_ADDR_PORT));
|
||||
}
|
||||
|
||||
void meson_encl_load_gamma(struct meson_drm *priv)
|
||||
{
|
||||
meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_R);
|
||||
meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_G);
|
||||
meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_B);
|
||||
|
||||
writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, L_GAMMA_CNTL_PORT_EN,
|
||||
priv->io_base + _REG(L_GAMMA_CNTL_PORT));
|
||||
}
|
||||
|
||||
void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv,
|
||||
const struct drm_display_mode *mode)
|
||||
{
|
||||
unsigned int max_pxcnt;
|
||||
unsigned int max_lncnt;
|
||||
unsigned int havon_begin;
|
||||
unsigned int havon_end;
|
||||
unsigned int vavon_bline;
|
||||
unsigned int vavon_eline;
|
||||
unsigned int hso_begin;
|
||||
unsigned int hso_end;
|
||||
unsigned int vso_begin;
|
||||
unsigned int vso_end;
|
||||
unsigned int vso_bline;
|
||||
unsigned int vso_eline;
|
||||
|
||||
max_pxcnt = mode->htotal - 1;
|
||||
max_lncnt = mode->vtotal - 1;
|
||||
havon_begin = mode->htotal - mode->hsync_start;
|
||||
havon_end = havon_begin + mode->hdisplay - 1;
|
||||
vavon_bline = mode->vtotal - mode->vsync_start;
|
||||
vavon_eline = vavon_bline + mode->vdisplay - 1;
|
||||
hso_begin = 0;
|
||||
hso_end = mode->hsync_end - mode->hsync_start;
|
||||
vso_begin = 0;
|
||||
vso_end = 0;
|
||||
vso_bline = 0;
|
||||
vso_eline = mode->vsync_end - mode->vsync_start;
|
||||
|
||||
meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL);
|
||||
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
|
||||
|
||||
writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE));
|
||||
writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN |
|
||||
ENCL_VIDEO_MODE_ADV_GAIN_HDTV |
|
||||
ENCL_SEL_GAMMA_RGB_IN, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
|
||||
|
||||
writel_relaxed(ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER,
|
||||
priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL));
|
||||
writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT));
|
||||
writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT));
|
||||
writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN));
|
||||
writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END));
|
||||
writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE));
|
||||
writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE));
|
||||
|
||||
writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN));
|
||||
writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END));
|
||||
writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN));
|
||||
writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END));
|
||||
writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE));
|
||||
writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE));
|
||||
writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK,
|
||||
priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL));
|
||||
|
||||
/* default black pattern */
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL));
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y));
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB));
|
||||
writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR));
|
||||
writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN));
|
||||
writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0,
|
||||
priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
|
||||
|
||||
writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
|
||||
|
||||
writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR));
|
||||
writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); /* Magic value */
|
||||
|
||||
writel_relaxed(L_DITH_CNTL_DITH10_EN, priv->io_base + _REG(L_DITH_CNTL_ADDR));
|
||||
|
||||
/* DE signal for TTL */
|
||||
writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR));
|
||||
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR));
|
||||
writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR));
|
||||
writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR));
|
||||
|
||||
/* DE signal for TTL */
|
||||
writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR));
|
||||
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR));
|
||||
writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR));
|
||||
writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR));
|
||||
|
||||
/* Hsync signal for TTL */
|
||||
if (mode->flags & DRM_MODE_FLAG_PHSYNC) {
|
||||
writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR));
|
||||
writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR));
|
||||
} else {
|
||||
writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR));
|
||||
writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR));
|
||||
}
|
||||
writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR));
|
||||
writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR));
|
||||
|
||||
/* Vsync signal for TTL */
|
||||
writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR));
|
||||
writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR));
|
||||
if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
|
||||
writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR));
|
||||
writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR));
|
||||
} else {
|
||||
writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR));
|
||||
writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR));
|
||||
}
|
||||
|
||||
/* DE signal */
|
||||
writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR));
|
||||
writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR));
|
||||
writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR));
|
||||
writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR));
|
||||
|
||||
/* Hsync signal */
|
||||
writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR));
|
||||
writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR));
|
||||
writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR));
|
||||
writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR));
|
||||
|
||||
/* Vsync signal */
|
||||
writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR));
|
||||
writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR));
|
||||
writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR));
|
||||
writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR));
|
||||
|
||||
writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR));
|
||||
writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2,
|
||||
priv->io_base + _REG(L_TCON_MISC_SEL_ADDR));
|
||||
|
||||
priv->venc.current_mode = MESON_VENC_MODE_MIPI_DSI;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set);
|
||||
|
||||
void meson_venci_cvbs_mode_set(struct meson_drm *priv,
|
||||
struct meson_cvbs_enci_mode *mode)
|
||||
{
|
||||
|
@ -1747,8 +1948,15 @@ unsigned int meson_venci_get_field(struct meson_drm *priv)
|
|||
|
||||
void meson_venc_enable_vsync(struct meson_drm *priv)
|
||||
{
|
||||
writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
|
||||
priv->io_base + _REG(VENC_INTCTRL));
|
||||
switch (priv->venc.current_mode) {
|
||||
case MESON_VENC_MODE_MIPI_DSI:
|
||||
writel_relaxed(VENC_INTCTRL_ENCP_LNRST_INT_EN,
|
||||
priv->io_base + _REG(VENC_INTCTRL));
|
||||
break;
|
||||
default:
|
||||
writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
|
||||
priv->io_base + _REG(VENC_INTCTRL));
|
||||
}
|
||||
regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
|
||||
}
|
||||
|
||||
|
|
|
@ -21,6 +21,7 @@ enum {
|
|||
MESON_VENC_MODE_CVBS_PAL,
|
||||
MESON_VENC_MODE_CVBS_NTSC,
|
||||
MESON_VENC_MODE_HDMI,
|
||||
MESON_VENC_MODE_MIPI_DSI,
|
||||
};
|
||||
|
||||
struct meson_cvbs_enci_mode {
|
||||
|
@ -47,6 +48,9 @@ struct meson_cvbs_enci_mode {
|
|||
unsigned int analog_sync_adj;
|
||||
};
|
||||
|
||||
/* LCD Encoder gamma setup */
|
||||
void meson_encl_load_gamma(struct meson_drm *priv);
|
||||
|
||||
/* HDMI Clock parameters */
|
||||
enum drm_mode_status
|
||||
meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
|
||||
|
@ -63,6 +67,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
|
|||
unsigned int ycrcb_map,
|
||||
bool yuv420_mode,
|
||||
const struct drm_display_mode *mode);
|
||||
void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv,
|
||||
const struct drm_display_mode *mode);
|
||||
unsigned int meson_venci_get_field(struct meson_drm *priv);
|
||||
|
||||
void meson_venc_enable_vsync(struct meson_drm *priv);
|
||||
|
|
|
@ -12,6 +12,8 @@
|
|||
struct drm_rect;
|
||||
struct meson_drm;
|
||||
|
||||
/* Mux VIU/VPP to ENCL */
|
||||
#define MESON_VIU_VPP_MUX_ENCL 0x0
|
||||
/* Mux VIU/VPP to ENCI */
|
||||
#define MESON_VIU_VPP_MUX_ENCI 0x5
|
||||
/* Mux VIU/VPP to ENCP */
|
||||
|
|
|
@ -1301,6 +1301,416 @@ static const struct panel_init_cmd starry_qfh032011_53g_init_cmd[] = {
|
|||
{},
|
||||
};
|
||||
|
||||
static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] = {
|
||||
_INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00),
|
||||
_INIT_DCS_CMD(0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x31, 0xD7, 0x2F, 0x36, 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11,
|
||||
0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x74, 0x33),
|
||||
_INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x72, 0x3C, 0xA3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xF5),
|
||||
_INIT_DCS_CMD(0xB4, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x63, 0x5C, 0x63, 0x5C, 0x01, 0x9E),
|
||||
_INIT_DCS_CMD(0xE9, 0xCD),
|
||||
_INIT_DCS_CMD(0xBA, 0x84),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xBC, 0x1B, 0x04),
|
||||
_INIT_DCS_CMD(0xBE, 0x20),
|
||||
_INIT_DCS_CMD(0xBF, 0xFC, 0xC4),
|
||||
_INIT_DCS_CMD(0xC0, 0x36, 0x36, 0x22, 0x11, 0x22, 0xA0, 0x61, 0x08, 0xF5, 0x03),
|
||||
_INIT_DCS_CMD(0xE9, 0xCC),
|
||||
_INIT_DCS_CMD(0xC7, 0x80),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xE9, 0xC6),
|
||||
_INIT_DCS_CMD(0xC8, 0x97),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01),
|
||||
_INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x33),
|
||||
_INIT_DCS_CMD(0xCC, 0x02),
|
||||
_INIT_DCS_CMD(0xE9, 0xC4),
|
||||
_INIT_DCS_CMD(0xD0, 0x03),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0C, 0xFF),
|
||||
_INIT_DCS_CMD(0xD2, 0x1F, 0x11, 0x1F),
|
||||
_INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x37, 0x47, 0x34, 0x3B, 0x12, 0x12, 0x03,
|
||||
0x03, 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x17, 0x94, 0x07, 0x94, 0x00, 0x00),
|
||||
_INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1A, 0x1A,
|
||||
0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
|
||||
_INIT_DCS_CMD(0xD6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1A, 0x1A,
|
||||
0x1B, 0x1B, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
|
||||
_INIT_DCS_CMD(0xD8, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA,
|
||||
0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0),
|
||||
_INIT_DCS_CMD(0xE0, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB,
|
||||
0xAB, 0x55, 0x5C, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, 0xAB, 0x55, 0x5C, 0x68, 0x73),
|
||||
_INIT_DCS_CMD(0xE7, 0x0E, 0x10, 0x10, 0x21, 0x2B, 0x9A, 0x02, 0x54, 0x9A, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, 0x10),
|
||||
_INIT_DCS_CMD(0xBD, 0x01),
|
||||
_INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11),
|
||||
_INIT_DCS_CMD(0xCB, 0x86),
|
||||
_INIT_DCS_CMD(0xD2, 0x3C, 0xFA),
|
||||
_INIT_DCS_CMD(0xE9, 0xC5),
|
||||
_INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40),
|
||||
_INIT_DCS_CMD(0xBD, 0x02),
|
||||
_INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0),
|
||||
_INIT_DCS_CMD(0xE7, 0xFE, 0x04, 0xFE, 0x04, 0xFE, 0x04, 0x03, 0x03, 0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00),
|
||||
_INIT_DCS_CMD(0xBD, 0x03),
|
||||
_INIT_DCS_CMD(0xE9, 0xC6),
|
||||
_INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xD8, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8,
|
||||
0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00),
|
||||
_INIT_DCS_CMD(0xBD, 0x00),
|
||||
_INIT_DCS_CMD(0xE9, 0xC4),
|
||||
_INIT_DCS_CMD(0xBA, 0x96),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xBD, 0x01),
|
||||
_INIT_DCS_CMD(0xE9, 0xC5),
|
||||
_INIT_DCS_CMD(0xBA, 0x4F),
|
||||
_INIT_DCS_CMD(0xE9, 0x3F),
|
||||
_INIT_DCS_CMD(0xBD, 0x00),
|
||||
_INIT_DCS_CMD(0x11),
|
||||
_INIT_DELAY_CMD(120),
|
||||
_INIT_DCS_CMD(0x29),
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct panel_init_cmd starry_ili9882t_init_cmd[] = {
|
||||
_INIT_DELAY_CMD(5),
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x01),
|
||||
_INIT_DCS_CMD(0x00, 0x42),
|
||||
_INIT_DCS_CMD(0x01, 0x11),
|
||||
_INIT_DCS_CMD(0x02, 0x00),
|
||||
_INIT_DCS_CMD(0x03, 0x00),
|
||||
|
||||
_INIT_DCS_CMD(0x04, 0x01),
|
||||
_INIT_DCS_CMD(0x05, 0x11),
|
||||
_INIT_DCS_CMD(0x06, 0x00),
|
||||
_INIT_DCS_CMD(0x07, 0x00),
|
||||
|
||||
_INIT_DCS_CMD(0x08, 0x80),
|
||||
_INIT_DCS_CMD(0x09, 0x81),
|
||||
_INIT_DCS_CMD(0x0A, 0x71),
|
||||
_INIT_DCS_CMD(0x0B, 0x00),
|
||||
|
||||
_INIT_DCS_CMD(0x0C, 0x00),
|
||||
_INIT_DCS_CMD(0x0E, 0x1A),
|
||||
|
||||
_INIT_DCS_CMD(0x24, 0x00),
|
||||
_INIT_DCS_CMD(0x25, 0x00),
|
||||
_INIT_DCS_CMD(0x26, 0x00),
|
||||
_INIT_DCS_CMD(0x27, 0x00),
|
||||
|
||||
_INIT_DCS_CMD(0x2C, 0xD4),
|
||||
_INIT_DCS_CMD(0xB9, 0x40),
|
||||
|
||||
_INIT_DCS_CMD(0xB0, 0x11),
|
||||
|
||||
_INIT_DCS_CMD(0xE6, 0x32),
|
||||
_INIT_DCS_CMD(0xD1, 0x30),
|
||||
|
||||
_INIT_DCS_CMD(0xD6, 0x55),
|
||||
|
||||
_INIT_DCS_CMD(0xD0, 0x01),
|
||||
_INIT_DCS_CMD(0xE3, 0x93),
|
||||
_INIT_DCS_CMD(0xE4, 0x00),
|
||||
_INIT_DCS_CMD(0xE5, 0x80),
|
||||
|
||||
_INIT_DCS_CMD(0x31, 0x07),
|
||||
_INIT_DCS_CMD(0x32, 0x07),
|
||||
_INIT_DCS_CMD(0x33, 0x07),
|
||||
_INIT_DCS_CMD(0x34, 0x07),
|
||||
_INIT_DCS_CMD(0x35, 0x07),
|
||||
_INIT_DCS_CMD(0x36, 0x01),
|
||||
_INIT_DCS_CMD(0x37, 0x00),
|
||||
_INIT_DCS_CMD(0x38, 0x28),
|
||||
_INIT_DCS_CMD(0x39, 0x29),
|
||||
_INIT_DCS_CMD(0x3A, 0x11),
|
||||
_INIT_DCS_CMD(0x3B, 0x13),
|
||||
_INIT_DCS_CMD(0x3C, 0x15),
|
||||
_INIT_DCS_CMD(0x3D, 0x17),
|
||||
_INIT_DCS_CMD(0x3E, 0x09),
|
||||
_INIT_DCS_CMD(0x3F, 0x0D),
|
||||
_INIT_DCS_CMD(0x40, 0x02),
|
||||
_INIT_DCS_CMD(0x41, 0x02),
|
||||
_INIT_DCS_CMD(0x42, 0x02),
|
||||
_INIT_DCS_CMD(0x43, 0x02),
|
||||
_INIT_DCS_CMD(0x44, 0x02),
|
||||
_INIT_DCS_CMD(0x45, 0x02),
|
||||
_INIT_DCS_CMD(0x46, 0x02),
|
||||
|
||||
_INIT_DCS_CMD(0x47, 0x07),
|
||||
_INIT_DCS_CMD(0x48, 0x07),
|
||||
_INIT_DCS_CMD(0x49, 0x07),
|
||||
_INIT_DCS_CMD(0x4A, 0x07),
|
||||
_INIT_DCS_CMD(0x4B, 0x07),
|
||||
_INIT_DCS_CMD(0x4C, 0x01),
|
||||
_INIT_DCS_CMD(0x4D, 0x00),
|
||||
_INIT_DCS_CMD(0x4E, 0x28),
|
||||
_INIT_DCS_CMD(0x4F, 0x29),
|
||||
_INIT_DCS_CMD(0x50, 0x10),
|
||||
_INIT_DCS_CMD(0x51, 0x12),
|
||||
_INIT_DCS_CMD(0x52, 0x14),
|
||||
_INIT_DCS_CMD(0x53, 0x16),
|
||||
_INIT_DCS_CMD(0x54, 0x08),
|
||||
_INIT_DCS_CMD(0x55, 0x0C),
|
||||
_INIT_DCS_CMD(0x56, 0x02),
|
||||
_INIT_DCS_CMD(0x57, 0x02),
|
||||
_INIT_DCS_CMD(0x58, 0x02),
|
||||
_INIT_DCS_CMD(0x59, 0x02),
|
||||
_INIT_DCS_CMD(0x5A, 0x02),
|
||||
_INIT_DCS_CMD(0x5B, 0x02),
|
||||
_INIT_DCS_CMD(0x5C, 0x02),
|
||||
|
||||
_INIT_DCS_CMD(0x61, 0x07),
|
||||
_INIT_DCS_CMD(0x62, 0x07),
|
||||
_INIT_DCS_CMD(0x63, 0x07),
|
||||
_INIT_DCS_CMD(0x64, 0x07),
|
||||
_INIT_DCS_CMD(0x65, 0x07),
|
||||
_INIT_DCS_CMD(0x66, 0x01),
|
||||
_INIT_DCS_CMD(0x67, 0x00),
|
||||
_INIT_DCS_CMD(0x68, 0x28),
|
||||
_INIT_DCS_CMD(0x69, 0x29),
|
||||
_INIT_DCS_CMD(0x6A, 0x16),
|
||||
_INIT_DCS_CMD(0x6B, 0x14),
|
||||
_INIT_DCS_CMD(0x6C, 0x12),
|
||||
_INIT_DCS_CMD(0x6D, 0x10),
|
||||
_INIT_DCS_CMD(0x6E, 0x0C),
|
||||
_INIT_DCS_CMD(0x6F, 0x08),
|
||||
_INIT_DCS_CMD(0x70, 0x02),
|
||||
_INIT_DCS_CMD(0x71, 0x02),
|
||||
_INIT_DCS_CMD(0x72, 0x02),
|
||||
_INIT_DCS_CMD(0x73, 0x02),
|
||||
_INIT_DCS_CMD(0x74, 0x02),
|
||||
_INIT_DCS_CMD(0x75, 0x02),
|
||||
_INIT_DCS_CMD(0x76, 0x02),
|
||||
|
||||
_INIT_DCS_CMD(0x77, 0x07),
|
||||
_INIT_DCS_CMD(0x78, 0x07),
|
||||
_INIT_DCS_CMD(0x79, 0x07),
|
||||
_INIT_DCS_CMD(0x7A, 0x07),
|
||||
_INIT_DCS_CMD(0x7B, 0x07),
|
||||
_INIT_DCS_CMD(0x7C, 0x01),
|
||||
_INIT_DCS_CMD(0x7D, 0x00),
|
||||
_INIT_DCS_CMD(0x7E, 0x28),
|
||||
_INIT_DCS_CMD(0x7F, 0x29),
|
||||
_INIT_DCS_CMD(0x80, 0x17),
|
||||
_INIT_DCS_CMD(0x81, 0x15),
|
||||
_INIT_DCS_CMD(0x82, 0x13),
|
||||
_INIT_DCS_CMD(0x83, 0x11),
|
||||
_INIT_DCS_CMD(0x84, 0x0D),
|
||||
_INIT_DCS_CMD(0x85, 0x09),
|
||||
_INIT_DCS_CMD(0x86, 0x02),
|
||||
_INIT_DCS_CMD(0x87, 0x07),
|
||||
_INIT_DCS_CMD(0x88, 0x07),
|
||||
_INIT_DCS_CMD(0x89, 0x07),
|
||||
_INIT_DCS_CMD(0x8A, 0x07),
|
||||
_INIT_DCS_CMD(0x8B, 0x07),
|
||||
_INIT_DCS_CMD(0x8C, 0x07),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x02),
|
||||
_INIT_DCS_CMD(0x29, 0x3A),
|
||||
_INIT_DCS_CMD(0x2A, 0x3B),
|
||||
|
||||
_INIT_DCS_CMD(0x06, 0x01),
|
||||
_INIT_DCS_CMD(0x07, 0x01),
|
||||
_INIT_DCS_CMD(0x08, 0x0C),
|
||||
_INIT_DCS_CMD(0x09, 0x44),
|
||||
|
||||
_INIT_DCS_CMD(0x3C, 0x0A),
|
||||
_INIT_DCS_CMD(0x39, 0x11),
|
||||
_INIT_DCS_CMD(0x3D, 0x00),
|
||||
_INIT_DCS_CMD(0x3A, 0x0C),
|
||||
_INIT_DCS_CMD(0x3B, 0x44),
|
||||
|
||||
_INIT_DCS_CMD(0x53, 0x1F),
|
||||
_INIT_DCS_CMD(0x5E, 0x40),
|
||||
_INIT_DCS_CMD(0x84, 0x00),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x03),
|
||||
_INIT_DCS_CMD(0x20, 0x01),
|
||||
_INIT_DCS_CMD(0x21, 0x3C),
|
||||
_INIT_DCS_CMD(0x22, 0xFA),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0A),
|
||||
_INIT_DCS_CMD(0xE0, 0x01),
|
||||
_INIT_DCS_CMD(0xE2, 0x01),
|
||||
_INIT_DCS_CMD(0xE5, 0x91),
|
||||
_INIT_DCS_CMD(0xE6, 0x3C),
|
||||
_INIT_DCS_CMD(0xE7, 0x00),
|
||||
_INIT_DCS_CMD(0xE8, 0xFA),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x12),
|
||||
_INIT_DCS_CMD(0x87, 0x2C),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x05),
|
||||
_INIT_DCS_CMD(0x73, 0xE5),
|
||||
_INIT_DCS_CMD(0x7F, 0x6B),
|
||||
_INIT_DCS_CMD(0x6D, 0xA4),
|
||||
_INIT_DCS_CMD(0x79, 0x54),
|
||||
_INIT_DCS_CMD(0x69, 0x97),
|
||||
_INIT_DCS_CMD(0x6A, 0x97),
|
||||
_INIT_DCS_CMD(0xA5, 0x3F),
|
||||
_INIT_DCS_CMD(0x61, 0xDA),
|
||||
_INIT_DCS_CMD(0xA7, 0xF1),
|
||||
_INIT_DCS_CMD(0x5F, 0x01),
|
||||
_INIT_DCS_CMD(0x62, 0x3F),
|
||||
_INIT_DCS_CMD(0x1D, 0x90),
|
||||
_INIT_DCS_CMD(0x86, 0x87),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x06),
|
||||
_INIT_DCS_CMD(0xC0, 0x80),
|
||||
_INIT_DCS_CMD(0xC1, 0x07),
|
||||
_INIT_DCS_CMD(0xCA, 0x58),
|
||||
_INIT_DCS_CMD(0xCB, 0x02),
|
||||
_INIT_DCS_CMD(0xCE, 0x58),
|
||||
_INIT_DCS_CMD(0xCF, 0x02),
|
||||
_INIT_DCS_CMD(0x67, 0x60),
|
||||
_INIT_DCS_CMD(0x10, 0x00),
|
||||
_INIT_DCS_CMD(0x92, 0x22),
|
||||
_INIT_DCS_CMD(0xD3, 0x08),
|
||||
_INIT_DCS_CMD(0xD6, 0x55),
|
||||
_INIT_DCS_CMD(0xDC, 0x38),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x08),
|
||||
_INIT_DCS_CMD(0xE0, 0x00, 0x10, 0x2A, 0x4D, 0x61, 0x56, 0x6A, 0x6E, 0x79, 0x76, 0x8F, 0x95, 0x98, 0xAE, 0xAA, 0xB2, 0xBB, 0xCE, 0xC6, 0xBD, 0xD5, 0xE2, 0xE8),
|
||||
_INIT_DCS_CMD(0xE1, 0x00, 0x10, 0x2A, 0x4D, 0x61, 0x56, 0x6A, 0x6E, 0x79, 0x76, 0x8F, 0x95, 0x98, 0xAE, 0xAA, 0xB2, 0xBB, 0xCE, 0xC6, 0xBD, 0xD5, 0xE2, 0xE8),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x04),
|
||||
_INIT_DCS_CMD(0xBA, 0x81),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0C),
|
||||
_INIT_DCS_CMD(0x00, 0x02),
|
||||
_INIT_DCS_CMD(0x01, 0x00),
|
||||
_INIT_DCS_CMD(0x02, 0x03),
|
||||
_INIT_DCS_CMD(0x03, 0x01),
|
||||
_INIT_DCS_CMD(0x04, 0x03),
|
||||
_INIT_DCS_CMD(0x05, 0x02),
|
||||
_INIT_DCS_CMD(0x06, 0x04),
|
||||
_INIT_DCS_CMD(0x07, 0x03),
|
||||
_INIT_DCS_CMD(0x08, 0x03),
|
||||
_INIT_DCS_CMD(0x09, 0x04),
|
||||
_INIT_DCS_CMD(0x0A, 0x04),
|
||||
_INIT_DCS_CMD(0x0B, 0x05),
|
||||
_INIT_DCS_CMD(0x0C, 0x04),
|
||||
_INIT_DCS_CMD(0x0D, 0x06),
|
||||
_INIT_DCS_CMD(0x0E, 0x05),
|
||||
_INIT_DCS_CMD(0x0F, 0x07),
|
||||
_INIT_DCS_CMD(0x10, 0x04),
|
||||
_INIT_DCS_CMD(0x11, 0x08),
|
||||
_INIT_DCS_CMD(0x12, 0x05),
|
||||
_INIT_DCS_CMD(0x13, 0x09),
|
||||
_INIT_DCS_CMD(0x14, 0x05),
|
||||
_INIT_DCS_CMD(0x15, 0x0A),
|
||||
_INIT_DCS_CMD(0x16, 0x06),
|
||||
_INIT_DCS_CMD(0x17, 0x0B),
|
||||
_INIT_DCS_CMD(0x18, 0x05),
|
||||
_INIT_DCS_CMD(0x19, 0x0C),
|
||||
_INIT_DCS_CMD(0x1A, 0x06),
|
||||
_INIT_DCS_CMD(0x1B, 0x0D),
|
||||
_INIT_DCS_CMD(0x1C, 0x06),
|
||||
_INIT_DCS_CMD(0x1D, 0x0E),
|
||||
_INIT_DCS_CMD(0x1E, 0x07),
|
||||
_INIT_DCS_CMD(0x1F, 0x0F),
|
||||
_INIT_DCS_CMD(0x20, 0x06),
|
||||
_INIT_DCS_CMD(0x21, 0x10),
|
||||
_INIT_DCS_CMD(0x22, 0x07),
|
||||
_INIT_DCS_CMD(0x23, 0x11),
|
||||
_INIT_DCS_CMD(0x24, 0x07),
|
||||
_INIT_DCS_CMD(0x25, 0x12),
|
||||
_INIT_DCS_CMD(0x26, 0x08),
|
||||
_INIT_DCS_CMD(0x27, 0x13),
|
||||
_INIT_DCS_CMD(0x28, 0x07),
|
||||
_INIT_DCS_CMD(0x29, 0x14),
|
||||
_INIT_DCS_CMD(0x2A, 0x08),
|
||||
_INIT_DCS_CMD(0x2B, 0x15),
|
||||
_INIT_DCS_CMD(0x2C, 0x08),
|
||||
_INIT_DCS_CMD(0x2D, 0x16),
|
||||
_INIT_DCS_CMD(0x2E, 0x09),
|
||||
_INIT_DCS_CMD(0x2F, 0x17),
|
||||
_INIT_DCS_CMD(0x30, 0x08),
|
||||
_INIT_DCS_CMD(0x31, 0x18),
|
||||
_INIT_DCS_CMD(0x32, 0x09),
|
||||
_INIT_DCS_CMD(0x33, 0x19),
|
||||
_INIT_DCS_CMD(0x34, 0x09),
|
||||
_INIT_DCS_CMD(0x35, 0x1A),
|
||||
_INIT_DCS_CMD(0x36, 0x0A),
|
||||
_INIT_DCS_CMD(0x37, 0x1B),
|
||||
_INIT_DCS_CMD(0x38, 0x0A),
|
||||
_INIT_DCS_CMD(0x39, 0x1C),
|
||||
_INIT_DCS_CMD(0x3A, 0x0A),
|
||||
_INIT_DCS_CMD(0x3B, 0x1D),
|
||||
_INIT_DCS_CMD(0x3C, 0x0A),
|
||||
_INIT_DCS_CMD(0x3D, 0x1E),
|
||||
_INIT_DCS_CMD(0x3E, 0x0A),
|
||||
_INIT_DCS_CMD(0x3F, 0x1F),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x04),
|
||||
_INIT_DCS_CMD(0xBA, 0x01),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0E),
|
||||
_INIT_DCS_CMD(0x02, 0x0C),
|
||||
_INIT_DCS_CMD(0x20, 0x10),
|
||||
_INIT_DCS_CMD(0x25, 0x16),
|
||||
_INIT_DCS_CMD(0x26, 0xE0),
|
||||
_INIT_DCS_CMD(0x27, 0x00),
|
||||
_INIT_DCS_CMD(0x29, 0x71),
|
||||
_INIT_DCS_CMD(0x2A, 0x46),
|
||||
_INIT_DCS_CMD(0x2B, 0x1F),
|
||||
_INIT_DCS_CMD(0x2D, 0xC7),
|
||||
_INIT_DCS_CMD(0x31, 0x02),
|
||||
_INIT_DCS_CMD(0x32, 0xDF),
|
||||
_INIT_DCS_CMD(0x33, 0x5A),
|
||||
_INIT_DCS_CMD(0x34, 0xC0),
|
||||
_INIT_DCS_CMD(0x35, 0x5A),
|
||||
_INIT_DCS_CMD(0x36, 0xC0),
|
||||
_INIT_DCS_CMD(0x38, 0x65),
|
||||
_INIT_DCS_CMD(0x80, 0x3E),
|
||||
_INIT_DCS_CMD(0x81, 0xA0),
|
||||
_INIT_DCS_CMD(0xB0, 0x01),
|
||||
_INIT_DCS_CMD(0xB1, 0xCC),
|
||||
_INIT_DCS_CMD(0xC0, 0x12),
|
||||
_INIT_DCS_CMD(0xC2, 0xCC),
|
||||
_INIT_DCS_CMD(0xC3, 0xCC),
|
||||
_INIT_DCS_CMD(0xC4, 0xCC),
|
||||
_INIT_DCS_CMD(0xC5, 0xCC),
|
||||
_INIT_DCS_CMD(0xC6, 0xCC),
|
||||
_INIT_DCS_CMD(0xC7, 0xCC),
|
||||
_INIT_DCS_CMD(0xC8, 0xCC),
|
||||
_INIT_DCS_CMD(0xC9, 0xCC),
|
||||
_INIT_DCS_CMD(0x30, 0x00),
|
||||
_INIT_DCS_CMD(0x00, 0x81),
|
||||
_INIT_DCS_CMD(0x08, 0x02),
|
||||
_INIT_DCS_CMD(0x09, 0x00),
|
||||
_INIT_DCS_CMD(0x07, 0x21),
|
||||
_INIT_DCS_CMD(0x04, 0x10),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x1E),
|
||||
_INIT_DCS_CMD(0x60, 0x00),
|
||||
_INIT_DCS_CMD(0x64, 0x00),
|
||||
_INIT_DCS_CMD(0x6D, 0x00),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0B),
|
||||
_INIT_DCS_CMD(0xA6, 0x44),
|
||||
_INIT_DCS_CMD(0xA7, 0xB6),
|
||||
_INIT_DCS_CMD(0xA8, 0x03),
|
||||
_INIT_DCS_CMD(0xA9, 0x03),
|
||||
_INIT_DCS_CMD(0xAA, 0x51),
|
||||
_INIT_DCS_CMD(0xAB, 0x51),
|
||||
_INIT_DCS_CMD(0xAC, 0x04),
|
||||
_INIT_DCS_CMD(0xBD, 0x92),
|
||||
_INIT_DCS_CMD(0xBE, 0xA1),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x05),
|
||||
_INIT_DCS_CMD(0x86, 0x87),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x06),
|
||||
_INIT_DCS_CMD(0x92, 0x22),
|
||||
|
||||
_INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x00),
|
||||
_INIT_DCS_CMD(0x11),
|
||||
_INIT_DELAY_CMD(120),
|
||||
_INIT_DCS_CMD(0x29),
|
||||
_INIT_DELAY_CMD(20),
|
||||
{},
|
||||
};
|
||||
|
||||
static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
|
||||
{
|
||||
return container_of(panel, struct boe_panel, base);
|
||||
|
@ -1698,6 +2108,62 @@ static const struct panel_desc starry_qfh032011_53g_desc = {
|
|||
.init_cmds = starry_qfh032011_53g_init_cmd,
|
||||
};
|
||||
|
||||
static const struct drm_display_mode starry_himax83102_j02_default_mode = {
|
||||
.clock = 161600,
|
||||
.hdisplay = 1200,
|
||||
.hsync_start = 1200 + 40,
|
||||
.hsync_end = 1200 + 40 + 20,
|
||||
.htotal = 1200 + 40 + 20 + 40,
|
||||
.vdisplay = 1920,
|
||||
.vsync_start = 1920 + 116,
|
||||
.vsync_end = 1920 + 116 + 8,
|
||||
.vtotal = 1920 + 116 + 8 + 12,
|
||||
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
||||
};
|
||||
|
||||
static const struct panel_desc starry_himax83102_j02_desc = {
|
||||
.modes = &starry_himax83102_j02_default_mode,
|
||||
.bpc = 8,
|
||||
.size = {
|
||||
.width_mm = 141,
|
||||
.height_mm = 226,
|
||||
},
|
||||
.lanes = 4,
|
||||
.format = MIPI_DSI_FMT_RGB888,
|
||||
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
|
||||
MIPI_DSI_MODE_LPM,
|
||||
.init_cmds = starry_himax83102_j02_init_cmd,
|
||||
.lp11_before_reset = true,
|
||||
};
|
||||
|
||||
static const struct drm_display_mode starry_ili9882t_default_mode = {
|
||||
.clock = 165280,
|
||||
.hdisplay = 1200,
|
||||
.hsync_start = 1200 + 32,
|
||||
.hsync_end = 1200 + 32 + 30,
|
||||
.htotal = 1200 + 32 + 30 + 32,
|
||||
.vdisplay = 1920,
|
||||
.vsync_start = 1920 + 68,
|
||||
.vsync_end = 1920 + 68 + 2,
|
||||
.vtotal = 1920 + 68 + 2 + 10,
|
||||
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
||||
};
|
||||
|
||||
static const struct panel_desc starry_ili9882t_desc = {
|
||||
.modes = &starry_ili9882t_default_mode,
|
||||
.bpc = 8,
|
||||
.size = {
|
||||
.width_mm = 141,
|
||||
.height_mm = 226,
|
||||
},
|
||||
.lanes = 4,
|
||||
.format = MIPI_DSI_FMT_RGB888,
|
||||
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
|
||||
MIPI_DSI_MODE_LPM,
|
||||
.init_cmds = starry_ili9882t_init_cmd,
|
||||
.lp11_before_reset = true,
|
||||
};
|
||||
|
||||
static int boe_panel_get_modes(struct drm_panel *panel,
|
||||
struct drm_connector *connector)
|
||||
{
|
||||
|
@ -1871,6 +2337,12 @@ static const struct of_device_id boe_of_match[] = {
|
|||
{ .compatible = "starry,2081101qfh032011-53g",
|
||||
.data = &starry_qfh032011_53g_desc
|
||||
},
|
||||
{ .compatible = "starry,himax83102-j02",
|
||||
.data = &starry_himax83102_j02_desc
|
||||
},
|
||||
{ .compatible = "starry,ili9882t",
|
||||
.data = &starry_ili9882t_desc
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, boe_of_match);
|
||||
|
|
|
@ -568,7 +568,7 @@ static const struct khadas_ts050_panel_cmd init_code[] = {
|
|||
{0xfb, 0x01},
|
||||
/* Select CMD1 */
|
||||
{0xff, 0x00},
|
||||
{0xd3, 0x05}, /* RGBMIPICTRL: VSYNC back porch = 5 */
|
||||
{0xd3, 0x22}, /* RGBMIPICTRL: VSYNC back porch = 34 */
|
||||
{0xd4, 0x04}, /* RGBMIPICTRL: VSYNC front porch = 4 */
|
||||
};
|
||||
|
||||
|
@ -717,15 +717,15 @@ static int khadas_ts050_panel_disable(struct drm_panel *panel)
|
|||
}
|
||||
|
||||
static const struct drm_display_mode default_mode = {
|
||||
.clock = 120000,
|
||||
.hdisplay = 1088,
|
||||
.hsync_start = 1088 + 104,
|
||||
.hsync_end = 1088 + 104 + 4,
|
||||
.htotal = 1088 + 104 + 4 + 127,
|
||||
.clock = 160000,
|
||||
.hdisplay = 1080,
|
||||
.hsync_start = 1080 + 117,
|
||||
.hsync_end = 1080 + 117 + 5,
|
||||
.htotal = 1080 + 117 + 5 + 160,
|
||||
.vdisplay = 1920,
|
||||
.vsync_start = 1920 + 4,
|
||||
.vsync_end = 1920 + 4 + 2,
|
||||
.vtotal = 1920 + 4 + 2 + 3,
|
||||
.vsync_end = 1920 + 4 + 3,
|
||||
.vtotal = 1920 + 4 + 3 + 31,
|
||||
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
|
||||
};
|
||||
|
||||
|
|
|
@ -3281,6 +3281,32 @@ static const struct panel_desc qishenglong_gopher2b_lcd = {
|
|||
.connector_type = DRM_MODE_CONNECTOR_DPI,
|
||||
};
|
||||
|
||||
static const struct display_timing rocktech_rk043fn48h_timing = {
|
||||
.pixelclock = { 6000000, 9000000, 12000000 },
|
||||
.hactive = { 480, 480, 480 },
|
||||
.hback_porch = { 8, 43, 43 },
|
||||
.hfront_porch = { 2, 8, 8 },
|
||||
.hsync_len = { 1, 1, 1 },
|
||||
.vactive = { 272, 272, 272 },
|
||||
.vback_porch = { 2, 12, 12 },
|
||||
.vfront_porch = { 1, 4, 4 },
|
||||
.vsync_len = { 1, 10, 10 },
|
||||
.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
|
||||
DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
|
||||
};
|
||||
|
||||
static const struct panel_desc rocktech_rk043fn48h = {
|
||||
.timings = &rocktech_rk043fn48h_timing,
|
||||
.num_timings = 1,
|
||||
.bpc = 8,
|
||||
.size = {
|
||||
.width = 95,
|
||||
.height = 54,
|
||||
},
|
||||
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
|
||||
.connector_type = DRM_MODE_CONNECTOR_DPI,
|
||||
};
|
||||
|
||||
static const struct display_timing rocktech_rk070er9427_timing = {
|
||||
.pixelclock = { 26400000, 33300000, 46800000 },
|
||||
.hactive = { 800, 800, 800 },
|
||||
|
@ -4320,6 +4346,9 @@ static const struct of_device_id platform_of_match[] = {
|
|||
}, {
|
||||
.compatible = "qishenglong,gopher2b-lcd",
|
||||
.data = &qishenglong_gopher2b_lcd,
|
||||
}, {
|
||||
.compatible = "rocktech,rk043fn48h",
|
||||
.data = &rocktech_rk043fn48h,
|
||||
}, {
|
||||
.compatible = "rocktech,rk070er9427",
|
||||
.data = &rocktech_rk070er9427,
|
||||
|
|
|
@ -6,6 +6,6 @@
|
|||
virtio-gpu-y := virtgpu_drv.o virtgpu_kms.o virtgpu_gem.o virtgpu_vram.o \
|
||||
virtgpu_display.o virtgpu_vq.o \
|
||||
virtgpu_fence.o virtgpu_object.o virtgpu_debugfs.o virtgpu_plane.o \
|
||||
virtgpu_ioctl.o virtgpu_prime.o virtgpu_trace_points.o
|
||||
virtgpu_ioctl.o virtgpu_prime.o virtgpu_trace_points.o virtgpu_submit.o
|
||||
|
||||
obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio-gpu.o
|
||||
|
|
|
@ -486,4 +486,8 @@ void virtio_gpu_vram_unmap_dma_buf(struct device *dev,
|
|||
struct sg_table *sgt,
|
||||
enum dma_data_direction dir);
|
||||
|
||||
/* virtgpu_submit.c */
|
||||
int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -38,36 +38,6 @@
|
|||
VIRTGPU_BLOB_FLAG_USE_SHAREABLE | \
|
||||
VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE)
|
||||
|
||||
static int virtio_gpu_fence_event_create(struct drm_device *dev,
|
||||
struct drm_file *file,
|
||||
struct virtio_gpu_fence *fence,
|
||||
uint32_t ring_idx)
|
||||
{
|
||||
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
|
||||
struct virtio_gpu_fence_event *e = NULL;
|
||||
int ret;
|
||||
|
||||
if (!(vfpriv->ring_idx_mask & BIT_ULL(ring_idx)))
|
||||
return 0;
|
||||
|
||||
e = kzalloc(sizeof(*e), GFP_KERNEL);
|
||||
if (!e)
|
||||
return -ENOMEM;
|
||||
|
||||
e->event.type = VIRTGPU_EVENT_FENCE_SIGNALED;
|
||||
e->event.length = sizeof(e->event);
|
||||
|
||||
ret = drm_event_reserve_init(dev, file, &e->base, &e->event);
|
||||
if (ret)
|
||||
goto free;
|
||||
|
||||
fence->e = e;
|
||||
return 0;
|
||||
free:
|
||||
kfree(e);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Must be called with &virtio_gpu_fpriv.struct_mutex held. */
|
||||
static void virtio_gpu_create_context_locked(struct virtio_gpu_device *vgdev,
|
||||
struct virtio_gpu_fpriv *vfpriv)
|
||||
|
@ -108,158 +78,6 @@ static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
|
|||
&virtio_gpu_map->offset);
|
||||
}
|
||||
|
||||
/*
|
||||
* Usage of execbuffer:
|
||||
* Relocations need to take into account the full VIRTIO_GPUDrawable size.
|
||||
* However, the command as passed from user space must *not* contain the initial
|
||||
* VIRTIO_GPUReleaseInfo struct (first XXX bytes)
|
||||
*/
|
||||
static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
{
|
||||
struct drm_virtgpu_execbuffer *exbuf = data;
|
||||
struct virtio_gpu_device *vgdev = dev->dev_private;
|
||||
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
|
||||
struct virtio_gpu_fence *out_fence;
|
||||
int ret;
|
||||
uint32_t *bo_handles = NULL;
|
||||
void __user *user_bo_handles = NULL;
|
||||
struct virtio_gpu_object_array *buflist = NULL;
|
||||
struct sync_file *sync_file;
|
||||
int out_fence_fd = -1;
|
||||
void *buf;
|
||||
uint64_t fence_ctx;
|
||||
uint32_t ring_idx;
|
||||
|
||||
fence_ctx = vgdev->fence_drv.context;
|
||||
ring_idx = 0;
|
||||
|
||||
if (vgdev->has_virgl_3d == false)
|
||||
return -ENOSYS;
|
||||
|
||||
if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
|
||||
return -EINVAL;
|
||||
|
||||
if ((exbuf->flags & VIRTGPU_EXECBUF_RING_IDX)) {
|
||||
if (exbuf->ring_idx >= vfpriv->num_rings)
|
||||
return -EINVAL;
|
||||
|
||||
if (!vfpriv->base_fence_ctx)
|
||||
return -EINVAL;
|
||||
|
||||
fence_ctx = vfpriv->base_fence_ctx;
|
||||
ring_idx = exbuf->ring_idx;
|
||||
}
|
||||
|
||||
virtio_gpu_create_context(dev, file);
|
||||
if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
|
||||
struct dma_fence *in_fence;
|
||||
|
||||
in_fence = sync_file_get_fence(exbuf->fence_fd);
|
||||
|
||||
if (!in_fence)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Wait if the fence is from a foreign context, or if the fence
|
||||
* array contains any fence from a foreign context.
|
||||
*/
|
||||
ret = 0;
|
||||
if (!dma_fence_match_context(in_fence, fence_ctx + ring_idx))
|
||||
ret = dma_fence_wait(in_fence, true);
|
||||
|
||||
dma_fence_put(in_fence);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
|
||||
out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
|
||||
if (out_fence_fd < 0)
|
||||
return out_fence_fd;
|
||||
}
|
||||
|
||||
if (exbuf->num_bo_handles) {
|
||||
bo_handles = kvmalloc_array(exbuf->num_bo_handles,
|
||||
sizeof(uint32_t), GFP_KERNEL);
|
||||
if (!bo_handles) {
|
||||
ret = -ENOMEM;
|
||||
goto out_unused_fd;
|
||||
}
|
||||
|
||||
user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
|
||||
if (copy_from_user(bo_handles, user_bo_handles,
|
||||
exbuf->num_bo_handles * sizeof(uint32_t))) {
|
||||
ret = -EFAULT;
|
||||
goto out_unused_fd;
|
||||
}
|
||||
|
||||
buflist = virtio_gpu_array_from_handles(file, bo_handles,
|
||||
exbuf->num_bo_handles);
|
||||
if (!buflist) {
|
||||
ret = -ENOENT;
|
||||
goto out_unused_fd;
|
||||
}
|
||||
kvfree(bo_handles);
|
||||
bo_handles = NULL;
|
||||
}
|
||||
|
||||
buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
|
||||
if (IS_ERR(buf)) {
|
||||
ret = PTR_ERR(buf);
|
||||
goto out_unused_fd;
|
||||
}
|
||||
|
||||
if (buflist) {
|
||||
ret = virtio_gpu_array_lock_resv(buflist);
|
||||
if (ret)
|
||||
goto out_memdup;
|
||||
}
|
||||
|
||||
out_fence = virtio_gpu_fence_alloc(vgdev, fence_ctx, ring_idx);
|
||||
if(!out_fence) {
|
||||
ret = -ENOMEM;
|
||||
goto out_unresv;
|
||||
}
|
||||
|
||||
ret = virtio_gpu_fence_event_create(dev, file, out_fence, ring_idx);
|
||||
if (ret)
|
||||
goto out_unresv;
|
||||
|
||||
if (out_fence_fd >= 0) {
|
||||
sync_file = sync_file_create(&out_fence->f);
|
||||
if (!sync_file) {
|
||||
dma_fence_put(&out_fence->f);
|
||||
ret = -ENOMEM;
|
||||
goto out_unresv;
|
||||
}
|
||||
|
||||
exbuf->fence_fd = out_fence_fd;
|
||||
fd_install(out_fence_fd, sync_file->file);
|
||||
}
|
||||
|
||||
virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
|
||||
vfpriv->ctx_id, buflist, out_fence);
|
||||
dma_fence_put(&out_fence->f);
|
||||
virtio_gpu_notify(vgdev);
|
||||
return 0;
|
||||
|
||||
out_unresv:
|
||||
if (buflist)
|
||||
virtio_gpu_array_unlock_resv(buflist);
|
||||
out_memdup:
|
||||
kvfree(buf);
|
||||
out_unused_fd:
|
||||
kvfree(bo_handles);
|
||||
if (buflist)
|
||||
virtio_gpu_array_put_free(buflist);
|
||||
|
||||
if (out_fence_fd >= 0)
|
||||
put_unused_fd(out_fence_fd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
{
|
||||
|
|
311
drivers/gpu/drm/virtio/virtgpu_submit.c
Normal file
311
drivers/gpu/drm/virtio/virtgpu_submit.c
Normal file
|
@ -0,0 +1,311 @@
|
|||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
* Copyright (C) 2015 Red Hat, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Authors:
|
||||
* Dave Airlie
|
||||
* Alon Levy
|
||||
*/
|
||||
|
||||
#include <linux/dma-fence-unwrap.h>
|
||||
#include <linux/file.h>
|
||||
#include <linux/sync_file.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include <drm/drm_file.h>
|
||||
#include <drm/virtgpu_drm.h>
|
||||
|
||||
#include "virtgpu_drv.h"
|
||||
|
||||
struct virtio_gpu_submit {
|
||||
struct virtio_gpu_object_array *buflist;
|
||||
struct drm_virtgpu_execbuffer *exbuf;
|
||||
struct virtio_gpu_fence *out_fence;
|
||||
struct virtio_gpu_fpriv *vfpriv;
|
||||
struct virtio_gpu_device *vgdev;
|
||||
struct sync_file *sync_file;
|
||||
struct drm_file *file;
|
||||
int out_fence_fd;
|
||||
u64 fence_ctx;
|
||||
u32 ring_idx;
|
||||
void *buf;
|
||||
};
|
||||
|
||||
static int virtio_gpu_do_fence_wait(struct virtio_gpu_submit *submit,
|
||||
struct dma_fence *in_fence)
|
||||
{
|
||||
u32 context = submit->fence_ctx + submit->ring_idx;
|
||||
|
||||
if (dma_fence_match_context(in_fence, context))
|
||||
return 0;
|
||||
|
||||
return dma_fence_wait(in_fence, true);
|
||||
}
|
||||
|
||||
static int virtio_gpu_dma_fence_wait(struct virtio_gpu_submit *submit,
|
||||
struct dma_fence *fence)
|
||||
{
|
||||
struct dma_fence_unwrap itr;
|
||||
struct dma_fence *f;
|
||||
int err;
|
||||
|
||||
dma_fence_unwrap_for_each(f, &itr, fence) {
|
||||
err = virtio_gpu_do_fence_wait(submit, f);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int virtio_gpu_fence_event_create(struct drm_device *dev,
|
||||
struct drm_file *file,
|
||||
struct virtio_gpu_fence *fence,
|
||||
u32 ring_idx)
|
||||
{
|
||||
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
|
||||
struct virtio_gpu_fence_event *e = NULL;
|
||||
int ret;
|
||||
|
||||
if (!(vfpriv->ring_idx_mask & BIT_ULL(ring_idx)))
|
||||
return 0;
|
||||
|
||||
e = kzalloc(sizeof(*e), GFP_KERNEL);
|
||||
if (!e)
|
||||
return -ENOMEM;
|
||||
|
||||
e->event.type = VIRTGPU_EVENT_FENCE_SIGNALED;
|
||||
e->event.length = sizeof(e->event);
|
||||
|
||||
ret = drm_event_reserve_init(dev, file, &e->base, &e->event);
|
||||
if (ret) {
|
||||
kfree(e);
|
||||
return ret;
|
||||
}
|
||||
|
||||
fence->e = e;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int virtio_gpu_init_submit_buflist(struct virtio_gpu_submit *submit)
|
||||
{
|
||||
struct drm_virtgpu_execbuffer *exbuf = submit->exbuf;
|
||||
u32 *bo_handles;
|
||||
|
||||
if (!exbuf->num_bo_handles)
|
||||
return 0;
|
||||
|
||||
bo_handles = kvmalloc_array(exbuf->num_bo_handles, sizeof(*bo_handles),
|
||||
GFP_KERNEL);
|
||||
if (!bo_handles)
|
||||
return -ENOMEM;
|
||||
|
||||
if (copy_from_user(bo_handles, u64_to_user_ptr(exbuf->bo_handles),
|
||||
exbuf->num_bo_handles * sizeof(*bo_handles))) {
|
||||
kvfree(bo_handles);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
submit->buflist = virtio_gpu_array_from_handles(submit->file, bo_handles,
|
||||
exbuf->num_bo_handles);
|
||||
if (!submit->buflist) {
|
||||
kvfree(bo_handles);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
kvfree(bo_handles);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void virtio_gpu_cleanup_submit(struct virtio_gpu_submit *submit)
|
||||
{
|
||||
if (!IS_ERR(submit->buf))
|
||||
kvfree(submit->buf);
|
||||
|
||||
if (submit->buflist)
|
||||
virtio_gpu_array_put_free(submit->buflist);
|
||||
|
||||
if (submit->out_fence_fd >= 0)
|
||||
put_unused_fd(submit->out_fence_fd);
|
||||
|
||||
if (submit->out_fence)
|
||||
dma_fence_put(&submit->out_fence->f);
|
||||
|
||||
if (submit->sync_file)
|
||||
fput(submit->sync_file->file);
|
||||
}
|
||||
|
||||
static void virtio_gpu_submit(struct virtio_gpu_submit *submit)
|
||||
{
|
||||
virtio_gpu_cmd_submit(submit->vgdev, submit->buf, submit->exbuf->size,
|
||||
submit->vfpriv->ctx_id, submit->buflist,
|
||||
submit->out_fence);
|
||||
virtio_gpu_notify(submit->vgdev);
|
||||
}
|
||||
|
||||
static void virtio_gpu_complete_submit(struct virtio_gpu_submit *submit)
|
||||
{
|
||||
submit->buf = NULL;
|
||||
submit->buflist = NULL;
|
||||
submit->sync_file = NULL;
|
||||
submit->out_fence = NULL;
|
||||
submit->out_fence_fd = -1;
|
||||
}
|
||||
|
||||
static int virtio_gpu_init_submit(struct virtio_gpu_submit *submit,
|
||||
struct drm_virtgpu_execbuffer *exbuf,
|
||||
struct drm_device *dev,
|
||||
struct drm_file *file,
|
||||
u64 fence_ctx, u32 ring_idx)
|
||||
{
|
||||
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
|
||||
struct virtio_gpu_device *vgdev = dev->dev_private;
|
||||
struct virtio_gpu_fence *out_fence;
|
||||
int err;
|
||||
|
||||
memset(submit, 0, sizeof(*submit));
|
||||
|
||||
out_fence = virtio_gpu_fence_alloc(vgdev, fence_ctx, ring_idx);
|
||||
if (!out_fence)
|
||||
return -ENOMEM;
|
||||
|
||||
err = virtio_gpu_fence_event_create(dev, file, out_fence, ring_idx);
|
||||
if (err) {
|
||||
dma_fence_put(&out_fence->f);
|
||||
return err;
|
||||
}
|
||||
|
||||
submit->out_fence = out_fence;
|
||||
submit->fence_ctx = fence_ctx;
|
||||
submit->ring_idx = ring_idx;
|
||||
submit->out_fence_fd = -1;
|
||||
submit->vfpriv = vfpriv;
|
||||
submit->vgdev = vgdev;
|
||||
submit->exbuf = exbuf;
|
||||
submit->file = file;
|
||||
|
||||
err = virtio_gpu_init_submit_buflist(submit);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
submit->buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
|
||||
if (IS_ERR(submit->buf))
|
||||
return PTR_ERR(submit->buf);
|
||||
|
||||
if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
|
||||
err = get_unused_fd_flags(O_CLOEXEC);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
submit->out_fence_fd = err;
|
||||
|
||||
submit->sync_file = sync_file_create(&out_fence->f);
|
||||
if (!submit->sync_file)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int virtio_gpu_wait_in_fence(struct virtio_gpu_submit *submit)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (submit->exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
|
||||
struct dma_fence *in_fence =
|
||||
sync_file_get_fence(submit->exbuf->fence_fd);
|
||||
if (!in_fence)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Wait if the fence is from a foreign context, or if the
|
||||
* fence array contains any fence from a foreign context.
|
||||
*/
|
||||
ret = virtio_gpu_dma_fence_wait(submit, in_fence);
|
||||
|
||||
dma_fence_put(in_fence);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void virtio_gpu_install_out_fence_fd(struct virtio_gpu_submit *submit)
|
||||
{
|
||||
if (submit->sync_file) {
|
||||
submit->exbuf->fence_fd = submit->out_fence_fd;
|
||||
fd_install(submit->out_fence_fd, submit->sync_file->file);
|
||||
}
|
||||
}
|
||||
|
||||
static int virtio_gpu_lock_buflist(struct virtio_gpu_submit *submit)
|
||||
{
|
||||
if (submit->buflist)
|
||||
return virtio_gpu_array_lock_resv(submit->buflist);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
{
|
||||
struct virtio_gpu_device *vgdev = dev->dev_private;
|
||||
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
|
||||
u64 fence_ctx = vgdev->fence_drv.context;
|
||||
struct drm_virtgpu_execbuffer *exbuf = data;
|
||||
struct virtio_gpu_submit submit;
|
||||
u32 ring_idx = 0;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!vgdev->has_virgl_3d)
|
||||
return -ENOSYS;
|
||||
|
||||
if (exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS)
|
||||
return ret;
|
||||
|
||||
if (exbuf->flags & VIRTGPU_EXECBUF_RING_IDX) {
|
||||
if (exbuf->ring_idx >= vfpriv->num_rings)
|
||||
return ret;
|
||||
|
||||
if (!vfpriv->base_fence_ctx)
|
||||
return ret;
|
||||
|
||||
fence_ctx = vfpriv->base_fence_ctx;
|
||||
ring_idx = exbuf->ring_idx;
|
||||
}
|
||||
|
||||
virtio_gpu_create_context(dev, file);
|
||||
|
||||
ret = virtio_gpu_init_submit(&submit, exbuf, dev, file,
|
||||
fence_ctx, ring_idx);
|
||||
if (ret)
|
||||
goto cleanup;
|
||||
|
||||
/*
|
||||
* Await in-fences in the end of the job submission path to
|
||||
* optimize the path by proceeding directly to the submission
|
||||
* to virtio after the waits.
|
||||
*/
|
||||
ret = virtio_gpu_wait_in_fence(&submit);
|
||||
if (ret)
|
||||
goto cleanup;
|
||||
|
||||
ret = virtio_gpu_lock_buflist(&submit);
|
||||
if (ret)
|
||||
goto cleanup;
|
||||
|
||||
virtio_gpu_submit(&submit);
|
||||
|
||||
/*
|
||||
* Set up usr-out data after submitting the job to optimize
|
||||
* the job submission path.
|
||||
*/
|
||||
virtio_gpu_install_out_fence_fd(&submit);
|
||||
virtio_gpu_complete_submit(&submit);
|
||||
cleanup:
|
||||
virtio_gpu_cleanup_submit(&submit);
|
||||
|
||||
return ret;
|
||||
}
|
Loading…
Reference in a new issue