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[libata] sata_mv: minor bug fixes, enhancements, and cleanups (prep for new EH)
* Continue replacing "CONSTANT & var" tests with "var & CONSTANT" * Don't clear EDMA_CFG_NCQ_GO_ON_ERR on Gen-IIE, where that bit does not exist * Set I/O Id field in descriptor, where present. Appears to work fine on all versions, even though queueing is still disabled. * call pci_set_mwi(), to (a) make sure cacheline size is set properly, and (b) enable MWI transactions * Remove never-used handling of coalescing interrupt bits (these events are always masked) Signed-off-by: Jeff Garzik <jeff@garzik.org>
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parent
c5d3e45a22
commit
4537deb5e9
1 changed files with 8 additions and 15 deletions
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@ -807,7 +807,7 @@ static int mv_stop_dma(struct ata_port *ap)
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u32 reg;
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int i, err = 0;
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if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
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if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
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/* Disable EDMA if active. The disable bit auto clears.
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*/
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writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
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@ -819,9 +819,9 @@ static int mv_stop_dma(struct ata_port *ap)
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/* now properly wait for the eDMA to stop */
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for (i = 1000; i > 0; i--) {
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reg = readl(port_mmio + EDMA_CMD_OFS);
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if (!(EDMA_EN & reg)) {
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if (!(reg & EDMA_EN))
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break;
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}
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udelay(100);
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}
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@ -974,7 +974,7 @@ static void mv_edma_cfg(struct ata_port *ap, struct mv_host_priv *hpriv,
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cfg |= (1 << 18); /* enab early completion */
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cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
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cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
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cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
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cfg &= ~(EDMA_CFG_NCQ); /* clear NCQ */
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}
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writelfl(cfg, port_mmio + EDMA_CFG_OFS);
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@ -1143,6 +1143,7 @@ static void mv_qc_prep(struct ata_queued_cmd *qc)
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flags |= CRQB_FLAG_READ;
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WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
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flags |= qc->tag << CRQB_TAG_SHIFT;
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flags |= qc->tag << CRQB_IOID_SHIFT; /* 50xx appears to ignore this*/
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/* get current queue index from hardware */
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in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
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@ -1236,6 +1237,8 @@ static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
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WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
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flags |= qc->tag << CRQB_TAG_SHIFT;
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flags |= qc->tag << CRQB_IOID_SHIFT; /* "I/O Id" is -really-
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what we use as our tag */
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/* get current queue index from hardware */
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in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
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@ -1525,7 +1528,6 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
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struct ata_host *host = dev_instance;
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unsigned int hc, handled = 0, n_hcs;
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void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
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struct mv_host_priv *hpriv;
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u32 irq_stat;
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irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
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@ -1547,16 +1549,6 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
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}
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}
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hpriv = host->private_data;
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if (IS_60XX(hpriv)) {
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/* deal with the interrupt coalescing bits */
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if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
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writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
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writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
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writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
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}
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}
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if (PCI_ERR & irq_stat) {
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printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
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readl(mmio + PCI_IRQ_CAUSE_OFS));
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@ -2474,6 +2466,7 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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mv_print_info(host);
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pci_set_master(pdev);
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pci_set_mwi(pdev);
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return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
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IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
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}
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