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clk: samsung: exynos5433: Add clocks for CMU_G3D domain

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This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi 2015-02-02 23:24:06 +09:00 committed by Sylwester Nawrocki
parent 4b8013554b
commit 453e519e5a
2 changed files with 152 additions and 0 deletions
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127
drivers/clk/samsung/clk-exynos5433.c
View file

@ -3120,3 +3120,130 @@ CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
exynos5433_cmu_bus_init(0);
exynos5433_cmu_bus_init(1);
exynos5433_cmu_bus_init(2);
/*
* Register offset definitions for CMU_G3D
*/
#define G3D_PLL_LOCK 0x0000
#define G3D_PLL_CON0 0x0100
#define G3D_PLL_CON1 0x0104
#define G3D_PLL_FREQ_DET 0x010c
#define MUX_SEL_G3D 0x0200
#define MUX_ENABLE_G3D 0x0300
#define MUX_STAT_G3D 0x0400
#define DIV_G3D 0x0600
#define DIV_G3D_PLL_FREQ_DET 0x0604
#define DIV_STAT_G3D 0x0700
#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
#define ENABLE_ACLK_G3D 0x0800
#define ENABLE_PCLK_G3D 0x0900
#define ENABLE_SCLK_G3D 0x0a00
#define ENABLE_IP_G3D0 0x0b00
#define ENABLE_IP_G3D1 0x0b04
#define CLKOUT_CMU_G3D 0x0c00
#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
#define CLK_STOPCTRL 0x1000
static unsigned long g3d_clk_regs[] __initdata = {
G3D_PLL_LOCK,
G3D_PLL_CON0,
G3D_PLL_CON1,
G3D_PLL_FREQ_DET,
MUX_SEL_G3D,
MUX_ENABLE_G3D,
MUX_STAT_G3D,
DIV_G3D,
DIV_G3D_PLL_FREQ_DET,
DIV_STAT_G3D,
DIV_STAT_G3D_PLL_FREQ_DET,
ENABLE_ACLK_G3D,
ENABLE_PCLK_G3D,
ENABLE_SCLK_G3D,
ENABLE_IP_G3D0,
ENABLE_IP_G3D1,
CLKOUT_CMU_G3D,
CLKOUT_CMU_G3D_DIV_STAT,
CLK_STOPCTRL,
};
/* list of all parent clock list */
PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
};
static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
/* MUX_SEL_G3D */
MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
MUX_SEL_G3D, 8, 1),
MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
MUX_SEL_G3D, 0, 1),
};
static struct samsung_div_clock g3d_div_clks[] __initdata = {
/* DIV_G3D */
DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
8, 2),
DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
4, 3),
DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
0, 3),
};
static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
/* ENABLE_ACLK_G3D */
GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
ENABLE_ACLK_G3D, 7, 0, 0),
GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
ENABLE_ACLK_G3D, 6, 0, 0),
GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
ENABLE_ACLK_G3D, 5, 0, 0),
GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
ENABLE_ACLK_G3D, 4, 0, 0),
GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
ENABLE_ACLK_G3D, 0, 0, 0),
/* ENABLE_PCLK_G3D */
GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
ENABLE_PCLK_G3D, 3, 0, 0),
GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
ENABLE_PCLK_G3D, 2, 0, 0),
GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_G3D */
GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
ENABLE_SCLK_G3D, 0, 0, 0),
};
static struct samsung_cmu_info g3d_cmu_info __initdata = {
.pll_clks = g3d_pll_clks,
.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
.mux_clks = g3d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
.div_clks = g3d_div_clks,
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
.nr_clk_ids = G3D_NR_CLK,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
};
static void __init exynos5433_cmu_g3d_init(struct device_node *np)
{
samsung_cmu_register_one(np, &g3d_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
exynos5433_cmu_g3d_init);

25
include/dt-bindings/clock/exynos5433.h
View file

@ -794,4 +794,29 @@
#define BUSx_NR_CLK 11
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_ACLK_G3D_400 2
#define CLK_MOUT_G3D_PLL 3
#define CLK_DIV_SCLK_HPM_G3D 4
#define CLK_DIV_PCLK_G3D 5
#define CLK_DIV_ACLK_G3D 6
#define CLK_ACLK_BTS_G3D1 7
#define CLK_ACLK_BTS_G3D0 8
#define CLK_ACLK_ASYNCAPBS_G3D 9
#define CLK_ACLK_ASYNCAPBM_G3D 10
#define CLK_ACLK_AHB2APB_G3DP 11
#define CLK_ACLK_G3DNP_150 12
#define CLK_ACLK_G3DND_600 13
#define CLK_ACLK_G3D 14
#define CLK_PCLK_BTS_G3D1 15
#define CLK_PCLK_BTS_G3D0 16
#define CLK_PCLK_PMU_G3D 17
#define CLK_PCLK_SYSREG_G3D 18
#define CLK_SCLK_HPM_G3D 19
#define G3D_NR_CLK 20
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */