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dmaengine: idxd: move idxd interrupt handling to mask instead of ignore
Switch driver to use MSIX mask and unmask instead of the ignore bit. When ignore bit is cleared, we must issue an MMIO read to ensure writes have all arrived and check and process any additional completions. The ignore bit does not queue up any pending MSIX interrupts. The mask bit however does. Use API call from interrupt subsystem to mask MSIX interrupt since the hardware does not have convenient mask bit register. Suggested-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/159319517621.70410.11816465052708900506.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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0d5c10b4c8
commit
4548a6ad3d
3 changed files with 13 additions and 46 deletions
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@ -6,6 +6,8 @@
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#include <linux/pci.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmaengine.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <uapi/linux/idxd.h>
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#include "../dmaengine.h"
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#include "idxd.h"
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@ -15,61 +17,28 @@ static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
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u32 *status);
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/* Interrupt control bits */
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int idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id)
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void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id)
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{
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struct pci_dev *pdev = idxd->pdev;
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int msixcnt = pci_msix_vec_count(pdev);
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union msix_perm perm;
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u32 offset;
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struct irq_data *data = irq_get_irq_data(idxd->msix_entries[vec_id].vector);
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if (vec_id < 0 || vec_id >= msixcnt)
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return -EINVAL;
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offset = idxd->msix_perm_offset + vec_id * 8;
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perm.bits = ioread32(idxd->reg_base + offset);
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perm.ignore = 1;
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iowrite32(perm.bits, idxd->reg_base + offset);
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return 0;
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pci_msi_mask_irq(data);
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}
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void idxd_mask_msix_vectors(struct idxd_device *idxd)
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{
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struct pci_dev *pdev = idxd->pdev;
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int msixcnt = pci_msix_vec_count(pdev);
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int i, rc;
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int i;
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for (i = 0; i < msixcnt; i++) {
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rc = idxd_mask_msix_vector(idxd, i);
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if (rc < 0)
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dev_warn(&pdev->dev,
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"Failed disabling msix vec %d\n", i);
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}
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for (i = 0; i < msixcnt; i++)
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idxd_mask_msix_vector(idxd, i);
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}
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int idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id)
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void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id)
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{
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struct pci_dev *pdev = idxd->pdev;
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int msixcnt = pci_msix_vec_count(pdev);
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union msix_perm perm;
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u32 offset;
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struct irq_data *data = irq_get_irq_data(idxd->msix_entries[vec_id].vector);
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if (vec_id < 0 || vec_id >= msixcnt)
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return -EINVAL;
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offset = idxd->msix_perm_offset + vec_id * 8;
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perm.bits = ioread32(idxd->reg_base + offset);
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perm.ignore = 0;
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iowrite32(perm.bits, idxd->reg_base + offset);
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/*
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* A readback from the device ensures that any previously generated
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* completion record writes are visible to software based on PCI
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* ordering rules.
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*/
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perm.bits = ioread32(idxd->reg_base + offset);
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return 0;
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pci_msi_unmask_irq(data);
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}
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void idxd_unmask_error_interrupts(struct idxd_device *idxd)
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@ -273,8 +273,8 @@ irqreturn_t idxd_wq_thread(int irq, void *data);
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void idxd_mask_error_interrupts(struct idxd_device *idxd);
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void idxd_unmask_error_interrupts(struct idxd_device *idxd);
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void idxd_mask_msix_vectors(struct idxd_device *idxd);
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int idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id);
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int idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id);
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void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id);
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void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id);
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/* device control */
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void idxd_device_init_reset(struct idxd_device *idxd);
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@ -260,8 +260,6 @@ irqreturn_t idxd_wq_thread(int irq, void *data)
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processed = idxd_desc_process(irq_entry);
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idxd_unmask_msix_vector(irq_entry->idxd, irq_entry->id);
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/* catch anything unprocessed after unmasking */
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processed += idxd_desc_process(irq_entry);
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if (processed == 0)
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return IRQ_NONE;
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