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drm/amd/powerplay: add set/get_power_profile_mode for Raven (v2)
The power profile allows the user to adjust the power state heuristics for clock level transitions. v2: squash in warning fix (Alex) Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Chengming Gui
Alex Deucher
parent
c9d66b361e
commit
45516e91c2
3 changed files with 99 additions and 7 deletions
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@ -35,6 +35,7 @@
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#include "smu10_hwmgr.h"
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#include "power_state.h"
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#include "soc15_common.h"
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#include "smu10.h"
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#define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
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@ -1200,6 +1201,94 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
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}
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}
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static int conv_power_profile_to_pplib_workload(int power_profile)
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{
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int pplib_workload = 0;
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switch (power_profile) {
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case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
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pplib_workload = WORKLOAD_DEFAULT_BIT;
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break;
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case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
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pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
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break;
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case PP_SMC_POWER_PROFILE_POWERSAVING:
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pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
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break;
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case PP_SMC_POWER_PROFILE_VIDEO:
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pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
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break;
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case PP_SMC_POWER_PROFILE_VR:
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pplib_workload = WORKLOAD_PPLIB_VR_BIT;
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break;
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case PP_SMC_POWER_PROFILE_COMPUTE:
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pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
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break;
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}
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return pplib_workload;
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}
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static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
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{
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uint32_t i, size = 0;
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static const uint8_t
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profile_mode_setting[6][4] = {{70, 60, 0, 0,},
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{70, 60, 1, 3,},
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{90, 60, 0, 0,},
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{70, 60, 0, 0,},
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{70, 90, 0, 0,},
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{30, 60, 0, 6,},
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};
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static const char *profile_name[6] = {
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"BOOTUP_DEFAULT",
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"3D_FULL_SCREEN",
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"POWER_SAVING",
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"VIDEO",
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"VR",
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"COMPUTE"};
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static const char *title[6] = {"NUM",
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"MODE_NAME",
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"BUSY_SET_POINT",
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"FPS",
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"USE_RLC_BUSY",
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"MIN_ACTIVE_LEVEL"};
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if (!buf)
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return -EINVAL;
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size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
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title[1], title[2], title[3], title[4], title[5]);
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for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
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size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
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i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
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profile_mode_setting[i][0], profile_mode_setting[i][1],
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profile_mode_setting[i][2], profile_mode_setting[i][3]);
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return size;
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}
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static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
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{
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int workload_type = 0;
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if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
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pr_err("Invalid power profile mode %ld\n", input[size]);
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return -EINVAL;
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}
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hwmgr->power_profile_mode = input[size];
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/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
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workload_type =
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conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
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smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
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1 << workload_type);
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return 0;
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}
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static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
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.backend_init = smu10_hwmgr_backend_init,
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.backend_fini = smu10_hwmgr_backend_fini,
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@ -1241,6 +1330,8 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
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.powergate_sdma = smu10_powergate_sdma,
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.set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
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.set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
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.get_power_profile_mode = smu10_get_power_profile_mode,
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.set_power_profile_mode = smu10_set_power_profile_mode,
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};
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int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
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@ -85,7 +85,6 @@
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#define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36
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#define PPSMC_Message_Count 0x37
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typedef uint16_t PPSMC_Result;
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typedef int PPSMC_Msg;
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@ -136,12 +136,14 @@
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#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT)
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/* Workload bits */
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#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
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#define WORKLOAD_PPLIB_VIDEO_BIT 2
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#define WORKLOAD_PPLIB_VR_BIT 3
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#define WORKLOAD_PPLIB_COMPUTE_BIT 4
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#define WORKLOAD_PPLIB_CUSTOM_BIT 5
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#define WORKLOAD_PPLIB_COUNT 6
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#define WORKLOAD_DEFAULT_BIT 0
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#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
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#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
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#define WORKLOAD_PPLIB_VIDEO_BIT 3
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#define WORKLOAD_PPLIB_VR_BIT 4
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#define WORKLOAD_PPLIB_COMPUTE_BIT 5
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#define WORKLOAD_PPLIB_CUSTOM_BIT 6
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#define WORKLOAD_PPLIB_COUNT 7
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typedef struct {
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/* MP1_EXT_SCRATCH0 */
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