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powerpc: Remove IBM405 Erratum #77
This erratum is dedicated to IBM 405GP and STB03xxx which are now gone. Remove this erratum. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/44dbc08e9034681eb28324cbabc086e97044c36c.1590079969.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
59fb463b48
commit
455531e9d8
10 changed files with 0 additions and 73 deletions
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@ -1,19 +0,0 @@
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#ifndef _ASM_POWERPC_ASM_405_H
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#define _ASM_POWERPC_ASM_405_H
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#include <asm/asm-const.h>
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#ifdef __KERNEL__
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#ifdef CONFIG_IBM405_ERR77
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/* Erratum #77 on the 405 means we need a sync or dcbt before every
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* stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this.
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*/
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#define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;)
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#define PPC405_ERR77_SYNC stringify_in_c(sync;)
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#else
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#define PPC405_ERR77(ra,rb)
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#define PPC405_ERR77_SYNC
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#endif
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#endif
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#endif /* _ASM_POWERPC_ASM_405_H */
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@ -10,7 +10,6 @@
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#include <linux/types.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#include <asm/asm-405.h>
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#define ATOMIC_INIT(i) { (i) }
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@ -47,7 +46,6 @@ static __inline__ void atomic_##op(int a, atomic_t *v) \
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__asm__ __volatile__( \
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"1: lwarx %0,0,%3 # atomic_" #op "\n" \
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#asm_op " %0,%2,%0\n" \
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PPC405_ERR77(0,%3) \
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" stwcx. %0,0,%3 \n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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@ -63,7 +61,6 @@ static inline int atomic_##op##_return_relaxed(int a, atomic_t *v) \
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__asm__ __volatile__( \
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"1: lwarx %0,0,%3 # atomic_" #op "_return_relaxed\n" \
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#asm_op " %0,%2,%0\n" \
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PPC405_ERR77(0, %3) \
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" stwcx. %0,0,%3\n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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@ -81,7 +78,6 @@ static inline int atomic_fetch_##op##_relaxed(int a, atomic_t *v) \
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__asm__ __volatile__( \
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"1: lwarx %0,0,%4 # atomic_fetch_" #op "_relaxed\n" \
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#asm_op " %1,%3,%0\n" \
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PPC405_ERR77(0, %4) \
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" stwcx. %1,0,%4\n" \
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" bne- 1b\n" \
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: "=&r" (res), "=&r" (t), "+m" (v->counter) \
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@ -130,7 +126,6 @@ static __inline__ void atomic_inc(atomic_t *v)
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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@ -146,7 +141,6 @@ static __inline__ int atomic_inc_return_relaxed(atomic_t *v)
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc_return_relaxed\n"
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" addic %0,%0,1\n"
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PPC405_ERR77(0, %2)
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" stwcx. %0,0,%2\n"
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" bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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@ -163,7 +157,6 @@ static __inline__ void atomic_dec(atomic_t *v)
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%2)\
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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@ -179,7 +172,6 @@ static __inline__ int atomic_dec_return_relaxed(atomic_t *v)
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec_return_relaxed\n"
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" addic %0,%0,-1\n"
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PPC405_ERR77(0, %2)
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" stwcx. %0,0,%2\n"
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" bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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@ -220,7 +212,6 @@ static __inline__ int atomic_fetch_add_unless(atomic_t *v, int a, int u)
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cmpw 0,%0,%3 \n\
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beq 2f \n\
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add %0,%2,%0 \n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%1 \n\
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bne- 1b \n"
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PPC_ATOMIC_EXIT_BARRIER
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@ -251,7 +242,6 @@ static __inline__ int atomic_inc_not_zero(atomic_t *v)
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cmpwi 0,%0,0\n\
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beq- 2f\n\
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addic %1,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %1,0,%2\n\
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bne- 1b\n"
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PPC_ATOMIC_EXIT_BARRIER
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@ -280,7 +270,6 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
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cmpwi %0,1\n\
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addi %0,%0,-1\n\
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blt- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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PPC_ATOMIC_EXIT_BARRIER
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@ -41,7 +41,6 @@
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#include <linux/compiler.h>
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#include <asm/asm-compat.h>
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#include <asm/synch.h>
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#include <asm/asm-405.h>
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/* PPC bit number conversion */
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#define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be))
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@ -73,7 +72,6 @@ static inline void fn(unsigned long mask, \
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prefix \
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"1:" PPC_LLARX(%0,0,%3,0) "\n" \
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stringify_in_c(op) "%0,%0,%2\n" \
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PPC405_ERR77(0,%3) \
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PPC_STLCX "%0,0,%3\n" \
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"bne- 1b\n" \
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: "=&r" (old), "+m" (*p) \
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@ -119,7 +117,6 @@ static inline unsigned long fn( \
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prefix \
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"1:" PPC_LLARX(%0,0,%3,eh) "\n" \
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stringify_in_c(op) "%1,%0,%2\n" \
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PPC405_ERR77(0,%3) \
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PPC_STLCX "%1,0,%3\n" \
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"bne- 1b\n" \
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postfix \
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@ -175,7 +172,6 @@ clear_bit_unlock_return_word(int nr, volatile unsigned long *addr)
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PPC_RELEASE_BARRIER
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"1:" PPC_LLARX(%0,0,%3,0) "\n"
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"andc %1,%0,%2\n"
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PPC405_ERR77(0,%3)
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PPC_STLCX "%1,0,%3\n"
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"bne- 1b\n"
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: "=&r" (old), "=&r" (t)
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@ -6,7 +6,6 @@
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#include <linux/compiler.h>
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#include <asm/synch.h>
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#include <linux/bug.h>
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#include <asm/asm-405.h>
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#ifdef __BIG_ENDIAN
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#define BITOFF_CAL(size, off) ((sizeof(u32) - size - off) * BITS_PER_BYTE)
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@ -29,7 +28,6 @@ static inline u32 __xchg_##type##sfx(volatile void *p, u32 val) \
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"1: lwarx %0,0,%3\n" \
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" andc %1,%0,%5\n" \
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" or %1,%1,%4\n" \
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PPC405_ERR77(0,%3) \
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" stwcx. %1,0,%3\n" \
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" bne- 1b\n" \
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: "=&r" (prev), "=&r" (tmp), "+m" (*(u32*)p) \
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@ -60,7 +58,6 @@ u32 __cmpxchg_##type##sfx(volatile void *p, u32 old, u32 new) \
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" bne- 2f\n" \
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" andc %1,%0,%6\n" \
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" or %1,%1,%5\n" \
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PPC405_ERR77(0,%3) \
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" stwcx. %1,0,%3\n" \
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" bne- 1b\n" \
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br2 \
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@ -92,7 +89,6 @@ __xchg_u32_local(volatile void *p, unsigned long val)
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 \n"
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PPC405_ERR77(0,%2)
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" stwcx. %3,0,%2 \n\
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bne- 1b"
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: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
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@ -109,7 +105,6 @@ __xchg_u32_relaxed(u32 *p, unsigned long val)
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__asm__ __volatile__(
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"1: lwarx %0,0,%2\n"
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PPC405_ERR77(0, %2)
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" stwcx. %3,0,%2\n"
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" bne- 1b"
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: "=&r" (prev), "+m" (*p)
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@ -127,7 +122,6 @@ __xchg_u64_local(volatile void *p, unsigned long val)
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 \n"
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PPC405_ERR77(0,%2)
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" stdcx. %3,0,%2 \n\
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bne- 1b"
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: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
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@ -144,7 +138,6 @@ __xchg_u64_relaxed(u64 *p, unsigned long val)
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__asm__ __volatile__(
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"1: ldarx %0,0,%2\n"
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PPC405_ERR77(0, %2)
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" stdcx. %3,0,%2\n"
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" bne- 1b"
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: "=&r" (prev), "+m" (*p)
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@ -229,7 +222,6 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
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"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
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cmpw 0,%0,%3\n\
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bne- 2f\n"
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PPC405_ERR77(0,%2)
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" stwcx. %4,0,%2\n\
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bne- 1b"
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PPC_ATOMIC_EXIT_BARRIER
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@ -252,7 +244,6 @@ __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
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"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
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cmpw 0,%0,%3\n\
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bne- 2f\n"
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PPC405_ERR77(0,%2)
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" stwcx. %4,0,%2\n\
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bne- 1b"
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"\n\
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@ -273,7 +264,6 @@ __cmpxchg_u32_relaxed(u32 *p, unsigned long old, unsigned long new)
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"1: lwarx %0,0,%2 # __cmpxchg_u32_relaxed\n"
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" cmpw 0,%0,%3\n"
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" bne- 2f\n"
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PPC405_ERR77(0, %2)
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" stwcx. %4,0,%2\n"
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" bne- 1b\n"
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"2:"
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@ -301,7 +291,6 @@ __cmpxchg_u32_acquire(u32 *p, unsigned long old, unsigned long new)
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"1: lwarx %0,0,%2 # __cmpxchg_u32_acquire\n"
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" cmpw 0,%0,%3\n"
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" bne- 2f\n"
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PPC405_ERR77(0, %2)
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" stwcx. %4,0,%2\n"
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" bne- 1b\n"
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PPC_ACQUIRE_BARRIER
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@ -8,14 +8,12 @@
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#include <asm/synch.h>
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#include <asm/asm-405.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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__asm__ __volatile ( \
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PPC_ATOMIC_ENTRY_BARRIER \
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"1: lwarx %0,0,%2\n" \
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insn \
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PPC405_ERR77(0, %2) \
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"2: stwcx. %1,0,%2\n" \
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"bne- 1b\n" \
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PPC_ATOMIC_EXIT_BARRIER \
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@ -82,7 +80,6 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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"1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\
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cmpw 0,%1,%4\n\
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bne- 3f\n"
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PPC405_ERR77(0,%3)
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"2: stwcx. %5,0,%3\n\
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bne- 1b\n"
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PPC_ATOMIC_EXIT_BARRIER
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@ -9,7 +9,6 @@
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#include <linux/sched.h>
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#include <linux/threads.h>
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#include <asm/mmu.h> /* For sub-arch specific PPC_PIN_SIZE */
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#include <asm/asm-405.h>
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#ifdef CONFIG_44x
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extern int icache_44x_need_flush;
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@ -23,7 +23,6 @@
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#endif
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#include <asm/synch.h>
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#include <asm/ppc-opcode.h>
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#include <asm/asm-405.h>
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#ifdef CONFIG_PPC64
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/* use 0x800000yy when locked, where yy == CPU number */
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@ -210,7 +209,6 @@ static inline long __arch_read_trylock(arch_rwlock_t *rw)
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__DO_SIGN_EXTEND
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" addic. %0,%0,1\n\
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ble- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b\n"
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PPC_ACQUIRE_BARRIER
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@ -234,7 +232,6 @@ static inline long __arch_write_trylock(arch_rwlock_t *rw)
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"1: " PPC_LWARX(%0,0,%2,1) "\n\
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cmpwi 0,%0,0\n\
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bne- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %1,0,%2\n\
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bne- 1b\n"
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PPC_ACQUIRE_BARRIER
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@ -292,7 +289,6 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
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PPC_RELEASE_BARRIER
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"1: lwarx %0,0,%1\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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: "=&r"(tmp)
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@ -28,7 +28,6 @@
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#include <asm/unistd.h>
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/asm-405.h>
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#include <asm/feature-fixups.h>
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#include <asm/barrier.h>
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#include <asm/kup.h>
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@ -541,9 +540,6 @@ syscall_exit_work:
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addi r12,r2,TI_FLAGS
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3: lwarx r8,0,r12
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andc r8,r8,r11
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#ifdef CONFIG_IBM405_ERR77
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dcbt 0,r12
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#endif
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stwcx. r8,0,r12
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bne- 3b
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@ -918,9 +914,6 @@ resume_kernel:
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addi r5,r2,TI_FLAGS
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0: lwarx r8,0,r5
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andc r8,r8,r11
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#ifdef CONFIG_IBM405_ERR77
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dcbt 0,r5
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#endif
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stwcx. r8,0,r5
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bne- 0b
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1:
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@ -997,7 +990,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
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mtspr SPRN_XER,r10
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mtctr r11
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PPC405_ERR77(0,r1)
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BEGIN_FTR_SECTION
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lwarx r11,0,r1
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
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@ -1066,7 +1058,6 @@ exc_exit_start:
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lwz r1,GPR1(r1)
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.globl exc_exit_restart_end
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exc_exit_restart_end:
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PPC405_ERR77_SYNC
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rfi
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b . /* prevent prefetch past rfi */
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@ -1109,7 +1100,6 @@ exc_exit_restart_end:
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lwz r11,_CTR(r1); \
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mtspr SPRN_XER,r10; \
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mtctr r11; \
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PPC405_ERR77(0,r1); \
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stwcx. r0,0,r1; /* to clear the reservation */ \
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lwz r11,_LINK(r1); \
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mtlr r11; \
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@ -1129,7 +1119,6 @@ exc_exit_restart_end:
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lwz r10,GPR10(r1); \
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lwz r11,GPR11(r1); \
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lwz r1,GPR1(r1); \
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PPC405_ERR77_SYNC; \
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exc_lvl_rfi; \
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b .; /* prevent prefetch past exc_lvl_rfi */
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@ -36,7 +36,6 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/export.h>
|
||||
#include <asm/asm-405.h>
|
||||
|
||||
#include "head_32.h"
|
||||
|
||||
|
|
@ -487,7 +486,6 @@ _ENTRY(saved_ksp_limit)
|
|||
lwz r12,GPR12(r11)
|
||||
lwz r10,crit_r10@l(0)
|
||||
lwz r11,crit_r11@l(0)
|
||||
PPC405_ERR77_SYNC
|
||||
rfci
|
||||
b .
|
||||
|
||||
|
|
@ -569,7 +567,6 @@ finish_tlb_load:
|
|||
mfspr r12, SPRN_SPRG_SCRATCH3
|
||||
mfspr r11, SPRN_SPRG_SCRATCH1
|
||||
mfspr r10, SPRN_SPRG_SCRATCH0
|
||||
PPC405_ERR77_SYNC
|
||||
rfi /* Should sync shadow TLBs */
|
||||
b . /* prevent prefetch past rfi */
|
||||
|
||||
|
|
|
|||
|
|
@ -69,12 +69,6 @@ config PPC4xx_GPIO
|
|||
help
|
||||
Enable gpiolib support for ppc40x based boards
|
||||
|
||||
# 40x errata/workaround config symbols, selected by the CPU models above
|
||||
|
||||
# All 405-based cores up until the 405GPR and 405EP have this errata.
|
||||
config IBM405_ERR77
|
||||
bool
|
||||
|
||||
config APM8018X
|
||||
bool "APM8018X"
|
||||
depends on 40x
|
||||
|
|
|
|||
Loading…
Reference in a new issue