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ARM: S3C64XX: Modified files for SPI consolidation work
As SPI platform devices are consolidated to plat-samsung, some corresponding changes are required in the respective machine folder. Setup files are added for SPI GPIO configurations and platform data initialization. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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6 changed files with 66 additions and 0 deletions
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@ -77,6 +77,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
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help
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Common setup code for S3C64XX SDHCI GPIO configurations
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config S3C64XX_SETUP_SPI
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bool
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help
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Common setup code for SPI GPIO configurations
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# S36400 Macchine support
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config MACH_SMDK6400
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@ -34,6 +34,7 @@ obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
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obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
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obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
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obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o
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# PM
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@ -115,6 +115,8 @@
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#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
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#define S3C_PA_RTC S3C64XX_PA_RTC
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#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
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#define S3C_PA_SPI0 S3C64XX_PA_SPI0
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#define S3C_PA_SPI1 S3C64XX_PA_SPI1
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#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
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#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
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45
arch/arm/mach-s3c64xx/setup-spi.c
Normal file
45
arch/arm/mach-s3c64xx/setup-spi.c
Normal file
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@ -0,0 +1,45 @@
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/* linux/arch/arm/mach-s3c64xx/setup-spi.c
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*
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* Copyright (C) 2011 Samsung Electronics Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <plat/gpio-cfg.h>
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#include <plat/s3c64xx-spi.h>
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#ifdef CONFIG_S3C64XX_DEV_SPI0
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struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.tx_st_done = 21,
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};
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int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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#ifdef CONFIG_S3C64XX_DEV_SPI1
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struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.tx_st_done = 21,
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};
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int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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@ -1498,6 +1498,9 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
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pd->num_cs = num_cs;
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pd->src_clk_nr = src_clk_nr;
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if (!pd->cfg_gpio)
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pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
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s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
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}
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#endif /* CONFIG_S3C64XX_DEV_SPI0 */
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@ -1537,6 +1540,9 @@ void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
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pd->num_cs = num_cs;
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pd->src_clk_nr = src_clk_nr;
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if (!pd->cfg_gpio)
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pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
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s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
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}
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#endif /* CONFIG_S3C64XX_DEV_SPI1 */
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@ -71,4 +71,11 @@ extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
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int src_clk_nr, int num_cs);
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extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
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int src_clk_nr, int num_cs);
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/* defined by architecture to configure gpio */
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extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
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extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
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extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
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extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
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#endif /* __S3C64XX_PLAT_SPI_H */
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