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RDMA/hns: Remove the num_qpc_timer variable
The bt number of qpc_timer of HIP09 increases compared with that of HIP08.
Therefore, qpc_timer_bt_num and num_qpc_timer do not match. As a result,
the driver may fail to allocate qpc_timer. So the driver needs to uniquely
uses qpc_timer_bt_num to represent the bt number of qpc_timer.
Fixes: 0e40dc2f70
("RDMA/hns: Add timer allocation support for hip08")
Link: https://lore.kernel.org/r/20220829105021.1427804-4-liangwenpeng@huawei.com
Signed-off-by: Yixing Liu <liuyixing1@huawei.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
parent
0c8b5d6268
commit
45baad7dd9
4 changed files with 3 additions and 5 deletions
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@ -730,7 +730,6 @@ struct hns_roce_caps {
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u32 num_qps;
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u32 num_pi_qps;
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u32 reserved_qps;
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int num_qpc_timer;
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u32 num_srqs;
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u32 max_wqes;
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u32 max_srq_wrs;
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@ -1977,7 +1977,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
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caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
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caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
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caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
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caps->qpc_timer_bt_num = HNS_ROCE_V2_MAX_QPC_TIMER_BT_NUM;
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caps->cqc_timer_bt_num = HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM;
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caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
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@ -2273,7 +2273,6 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
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caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
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caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
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caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg);
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caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer);
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caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
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caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
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caps->num_aeq_vectors = resp_a->num_aeq_vectors;
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@ -36,11 +36,11 @@
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#include <linux/bitops.h>
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#define HNS_ROCE_V2_MAX_QP_NUM 0x1000
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#define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
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#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
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#define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
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#define HNS_ROCE_V2_MAX_SRQ_SGE 64
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#define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
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#define HNS_ROCE_V2_MAX_QPC_TIMER_BT_NUM 0x100
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#define HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM 0x100
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#define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
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#define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
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@ -725,7 +725,7 @@ static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
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ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
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HEM_TYPE_QPC_TIMER,
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hr_dev->caps.qpc_timer_entry_sz,
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hr_dev->caps.num_qpc_timer, 1);
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hr_dev->caps.qpc_timer_bt_num, 1);
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if (ret) {
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dev_err(dev,
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"Failed to init QPC timer memory, aborting.\n");
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