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dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. Add clock indices and binding documentation for CMU_AUD. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-2-semen.protsenko@linaro.org
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2 changed files with 86 additions and 1 deletions
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@ -33,6 +33,7 @@ properties:
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enum:
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- samsung,exynos850-cmu-top
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- samsung,exynos850-cmu-apm
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- samsung,exynos850-cmu-aud
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- samsung,exynos850-cmu-cmgp
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- samsung,exynos850-cmu-core
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- samsung,exynos850-cmu-dpu
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@ -88,6 +89,24 @@ allOf:
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- const: oscclk
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- const: dout_clkcmu_apm_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-aud
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: AUD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_aud
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- if:
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properties:
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compatible:
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@ -58,7 +58,10 @@
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#define CLK_MOUT_CLKCMU_APM_BUS 46
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#define CLK_DOUT_CLKCMU_APM_BUS 47
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#define CLK_GOUT_CLKCMU_APM_BUS 48
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#define TOP_NR_CLK 49
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#define CLK_MOUT_AUD 49
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#define CLK_GOUT_AUD 50
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#define CLK_DOUT_AUD 51
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#define TOP_NR_CLK 52
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/* CMU_APM */
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#define CLK_RCO_I3C_PMIC 1
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@ -87,6 +90,69 @@
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#define CLK_GOUT_SYSREG_APM_PCLK 24
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#define APM_NR_CLK 25
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/* CMU_AUD */
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#define CLK_DOUT_AUD_AUDIF 1
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#define CLK_DOUT_AUD_BUSD 2
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#define CLK_DOUT_AUD_BUSP 3
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#define CLK_DOUT_AUD_CNT 4
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#define CLK_DOUT_AUD_CPU 5
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#define CLK_DOUT_AUD_CPU_ACLK 6
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#define CLK_DOUT_AUD_CPU_PCLKDBG 7
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#define CLK_DOUT_AUD_FM 8
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#define CLK_DOUT_AUD_FM_SPDY 9
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#define CLK_DOUT_AUD_MCLK 10
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#define CLK_DOUT_AUD_UAIF0 11
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#define CLK_DOUT_AUD_UAIF1 12
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#define CLK_DOUT_AUD_UAIF2 13
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#define CLK_DOUT_AUD_UAIF3 14
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#define CLK_DOUT_AUD_UAIF4 15
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#define CLK_DOUT_AUD_UAIF5 16
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#define CLK_DOUT_AUD_UAIF6 17
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#define CLK_FOUT_AUD_PLL 18
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#define CLK_GOUT_AUD_ABOX_ACLK 19
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#define CLK_GOUT_AUD_ASB_CCLK 20
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#define CLK_GOUT_AUD_CA32_CCLK 21
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#define CLK_GOUT_AUD_CNT_BCLK 22
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#define CLK_GOUT_AUD_CODEC_MCLK 23
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#define CLK_GOUT_AUD_DAP_CCLK 24
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#define CLK_GOUT_AUD_GPIO_PCLK 25
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#define CLK_GOUT_AUD_PPMU_ACLK 26
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#define CLK_GOUT_AUD_PPMU_PCLK 27
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#define CLK_GOUT_AUD_SPDY_BCLK 28
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#define CLK_GOUT_AUD_SYSMMU_CLK 29
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#define CLK_GOUT_AUD_SYSREG_PCLK 30
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#define CLK_GOUT_AUD_TZPC_PCLK 31
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#define CLK_GOUT_AUD_UAIF0_BCLK 32
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#define CLK_GOUT_AUD_UAIF1_BCLK 33
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#define CLK_GOUT_AUD_UAIF2_BCLK 34
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#define CLK_GOUT_AUD_UAIF3_BCLK 35
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#define CLK_GOUT_AUD_UAIF4_BCLK 36
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#define CLK_GOUT_AUD_UAIF5_BCLK 37
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#define CLK_GOUT_AUD_UAIF6_BCLK 38
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#define CLK_GOUT_AUD_WDT_PCLK 39
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#define CLK_MOUT_AUD_CPU 40
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#define CLK_MOUT_AUD_CPU_HCH 41
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#define CLK_MOUT_AUD_CPU_USER 42
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#define CLK_MOUT_AUD_FM 43
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#define CLK_MOUT_AUD_PLL 44
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#define CLK_MOUT_AUD_TICK_USB_USER 45
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#define CLK_MOUT_AUD_UAIF0 46
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#define CLK_MOUT_AUD_UAIF1 47
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#define CLK_MOUT_AUD_UAIF2 48
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#define CLK_MOUT_AUD_UAIF3 49
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#define CLK_MOUT_AUD_UAIF4 50
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#define CLK_MOUT_AUD_UAIF5 51
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#define CLK_MOUT_AUD_UAIF6 52
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#define IOCLK_AUDIOCDCLK0 53
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#define IOCLK_AUDIOCDCLK1 54
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#define IOCLK_AUDIOCDCLK2 55
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#define IOCLK_AUDIOCDCLK3 56
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#define IOCLK_AUDIOCDCLK4 57
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#define IOCLK_AUDIOCDCLK5 58
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#define IOCLK_AUDIOCDCLK6 59
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#define TICK_USB 60
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#define AUD_NR_CLK 61
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/* CMU_CMGP */
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#define CLK_RCO_CMGP 1
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#define CLK_MOUT_CMGP_ADC 2
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