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perf vendors events arm64: Arm Cortex-A77
Add PMU events for Arm Cortex-A77 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a77.json which is based on PMU event descriptions from the Arm Cortex-A77 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-9-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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parent
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json
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[
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{
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"ArchStdEvent": "BR_MIS_PRED"
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},
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{
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"ArchStdEvent": "BR_PRED"
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},
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{
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"ArchStdEvent": "BR_IMMED_SPEC"
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},
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{
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"ArchStdEvent": "BR_RETURN_SPEC"
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},
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{
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"ArchStdEvent": "BR_INDIRECT_SPEC"
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}
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]
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json
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[
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{
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"ArchStdEvent": "CPU_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS"
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},
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{
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"ArchStdEvent": "BUS_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR"
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}
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]
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143
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
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143
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json
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@ -0,0 +1,143 @@
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[
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L2D_CACHE_ALLOCATE"
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},
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{
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"ArchStdEvent": "L1D_TLB"
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},
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{
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"ArchStdEvent": "L1I_TLB"
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},
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{
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"ArchStdEvent": "L3D_CACHE_ALLOCATE"
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},
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{
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"ArchStdEvent": "L3D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L3D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L2D_TLB"
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},
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{
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"ArchStdEvent": "DTLB_WALK"
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},
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{
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"ArchStdEvent": "ITLB_WALK"
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},
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{
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"ArchStdEvent": "LL_CACHE_RD"
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},
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{
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"ArchStdEvent": "LL_CACHE_MISS_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_INNER"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L1D_TLB_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_TLB_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_WR"
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},
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{
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"ArchStdEvent": "L3D_CACHE_RD"
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}
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]
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@ -0,0 +1,47 @@
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[
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{
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"ArchStdEvent": "EXC_TAKEN"
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},
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{
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"ArchStdEvent": "MEMORY_ERROR"
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},
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{
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"ArchStdEvent": "EXC_UNDEF"
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},
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{
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"ArchStdEvent": "EXC_SVC"
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},
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{
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"ArchStdEvent": "EXC_PABORT"
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},
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{
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"ArchStdEvent": "EXC_DABORT"
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},
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{
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"ArchStdEvent": "EXC_IRQ"
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},
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{
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"ArchStdEvent": "EXC_FIQ"
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},
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{
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"ArchStdEvent": "EXC_SMC"
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},
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{
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"ArchStdEvent": "EXC_HVC"
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},
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{
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"ArchStdEvent": "EXC_TRAP_PABORT"
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},
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{
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"ArchStdEvent": "EXC_TRAP_DABORT"
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},
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{
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"ArchStdEvent": "EXC_TRAP_OTHER"
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},
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{
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"ArchStdEvent": "EXC_TRAP_IRQ"
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},
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{
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"ArchStdEvent": "EXC_TRAP_FIQ"
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}
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]
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[
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{
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"ArchStdEvent": "SW_INCR"
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},
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{
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"ArchStdEvent": "INST_RETIRED"
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},
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{
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"ArchStdEvent": "EXC_RETURN"
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},
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{
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"ArchStdEvent": "CID_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "INST_SPEC"
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},
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{
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"ArchStdEvent": "TTBR_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "BR_RETIRED"
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},
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{
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"ArchStdEvent": "BR_MIS_PRED_RETIRED"
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},
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{
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"ArchStdEvent": "LDREX_SPEC"
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},
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{
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"ArchStdEvent": "STREX_PASS_SPEC"
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},
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{
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"ArchStdEvent": "STREX_FAIL_SPEC"
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},
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{
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"ArchStdEvent": "STREX_SPEC"
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},
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{
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"ArchStdEvent": "LD_SPEC"
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},
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{
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"ArchStdEvent": "ST_SPEC"
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},
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{
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"ArchStdEvent": "LDST_SPEC"
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},
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{
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"ArchStdEvent": "DP_SPEC"
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},
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{
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"ArchStdEvent": "ASE_SPEC"
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},
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{
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"ArchStdEvent": "VFP_SPEC"
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},
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{
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"ArchStdEvent": "PC_WRITE_SPEC"
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},
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{
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"ArchStdEvent": "CRYPTO_SPEC"
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},
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{
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"ArchStdEvent": "ISB_SPEC"
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},
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{
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"ArchStdEvent": "DSB_SPEC"
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},
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{
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"ArchStdEvent": "DMB_SPEC"
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},
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{
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"ArchStdEvent": "RC_LD_SPEC"
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},
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{
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"ArchStdEvent": "RC_ST_SPEC"
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}
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]
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23
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
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23
tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json
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[
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{
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"ArchStdEvent": "MEM_ACCESS"
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},
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{
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"ArchStdEvent": "REMOTE_ACCESS"
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},
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{
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"ArchStdEvent": "MEM_ACCESS_RD"
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},
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{
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"ArchStdEvent": "MEM_ACCESS_WR"
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},
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{
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"ArchStdEvent": "UNALIGNED_LD_SPEC"
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},
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{
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"ArchStdEvent": "UNALIGNED_ST_SPEC"
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},
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{
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"ArchStdEvent": "UNALIGNED_LDST_SPEC"
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}
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]
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[
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{
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"ArchStdEvent": "STALL_FRONTEND"
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},
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{
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"ArchStdEvent": "STALL_BACKEND"
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}
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]
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0x00000000410fd0a0,v1,arm/cortex-a75,core
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0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
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0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
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0x00000000410fd0d0,v1,arm/cortex-a77,core
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0x00000000410fd400,v1,arm/neoverse-v1,core
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0x00000000410fd460,v1,arm/cortex-a510,core
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0x00000000410fd490,v1,arm/neoverse-n2,core
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