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Merge branch 'icc-sm8650' into icc-next

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* icc-sm8650
  dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm SM8650 SoC
  interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC
  dt-bindings: interconnect: qcom-bwmon: document SM8650 BWMONs

This covers the RPMh Network-On-Chip Interconnect bindings
and driver for the interconnect framework.

As reported for earlier Interconnect drivers, the IDs
for multi-rsc voting has been removed from this driver
so the proper solution can be developed without having
to remove entries later on.

Link: https://lore.kernel.org/r/20231123-topic-sm8650-upstream-interconnect-v2-0-7e050874f59b@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov 2023-11-24 00:19:29 +02:00
commit 45db9b8416
7 changed files with 2120 additions and 0 deletions
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2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
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@ -32,6 +32,7 @@ properties:
- qcom,sm6350-llcc-bwmon
- qcom,sm8250-cpu-bwmon
- qcom,sm8550-cpu-bwmon
- qcom,sm8650-cpu-bwmon
- const: qcom,sdm845-bwmon # BWMON v4, unified register space
- items:
- enum:
@ -40,6 +41,7 @@ properties:
- qcom,sm6350-cpu-bwmon
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon
- qcom,sm8650-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon # BWMON v5
- const: qcom,sdm845-llcc-bwmon # BWMON v5

136
Documentation/devicetree/bindings/interconnect/qcom,sm8650-rpmh.yaml Normal file
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@ -0,0 +1,136 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
properties:
compatible:
enum:
- qcom,sm8650-aggre1-noc
- qcom,sm8650-aggre2-noc
- qcom,sm8650-clk-virt
- qcom,sm8650-cnoc-main
- qcom,sm8650-config-noc
- qcom,sm8650-gem-noc
- qcom,sm8650-lpass-ag-noc
- qcom,sm8650-lpass-lpiaon-noc
- qcom,sm8650-lpass-lpicx-noc
- qcom,sm8650-mc-virt
- qcom,sm8650-mmss-noc
- qcom,sm8650-nsp-noc
- qcom,sm8650-pcie-anoc
- qcom,sm8650-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-clk-virt
- qcom,sm8650-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre1-noc
- qcom,sm8650-aggre2-noc
- qcom,sm8650-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
clk_virt: interconnect-0 {
compatible = "qcom,sm8650-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8650-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

9
drivers/interconnect/qcom/Kconfig
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@ -245,5 +245,14 @@ config INTERCONNECT_QCOM_SM8550
This is a driver for the Qualcomm Network-on-Chip on SM8550-based
platforms.
config INTERCONNECT_QCOM_SM8650
tristate "Qualcomm SM8650 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on SM8650-based
platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate

2
drivers/interconnect/qcom/Makefile
View file

@ -30,6 +30,7 @@ qnoc-sm8250-objs := sm8250.o
qnoc-sm8350-objs := sm8350.o
qnoc-sm8450-objs := sm8450.o
qnoc-sm8550-objs := sm8550.o
qnoc-sm8650-objs := sm8650.o
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@ -59,4 +60,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8650) += qnoc-sm8650.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o

1674
drivers/interconnect/qcom/sm8650.c Normal file
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143
drivers/interconnect/qcom/sm8650.h Normal file
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@ -0,0 +1,143 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SM8650 interconnect IDs
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H
#define SM8650_MASTER_A1NOC_SNOC 0
#define SM8650_MASTER_A2NOC_SNOC 1
#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2
#define SM8650_MASTER_APPSS_PROC 3
#define SM8650_MASTER_CAMNOC_HF 4
#define SM8650_MASTER_CAMNOC_ICP 5
#define SM8650_MASTER_CAMNOC_SF 6
#define SM8650_MASTER_CDSP_HCP 7
#define SM8650_MASTER_CDSP_PROC 8
#define SM8650_MASTER_CNOC_CFG 9
#define SM8650_MASTER_CNOC_MNOC_CFG 10
#define SM8650_MASTER_COMPUTE_NOC 11
#define SM8650_MASTER_CRYPTO 12
#define SM8650_MASTER_GEM_NOC_CNOC 13
#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14
#define SM8650_MASTER_GFX3D 15
#define SM8650_MASTER_GIC 16
#define SM8650_MASTER_GPU_TCU 17
#define SM8650_MASTER_IPA 18
#define SM8650_MASTER_LLCC 19
#define SM8650_MASTER_LPASS_GEM_NOC 20
#define SM8650_MASTER_LPASS_LPINOC 21
#define SM8650_MASTER_LPASS_PROC 22
#define SM8650_MASTER_LPIAON_NOC 23
#define SM8650_MASTER_MDP 24
#define SM8650_MASTER_MNOC_HF_MEM_NOC 25
#define SM8650_MASTER_MNOC_SF_MEM_NOC 26
#define SM8650_MASTER_MSS_PROC 27
#define SM8650_MASTER_PCIE_0 28
#define SM8650_MASTER_PCIE_1 29
#define SM8650_MASTER_PCIE_ANOC_CFG 30
#define SM8650_MASTER_QDSS_BAM 31
#define SM8650_MASTER_QDSS_ETR 32
#define SM8650_MASTER_QDSS_ETR_1 33
#define SM8650_MASTER_QSPI_0 34
#define SM8650_MASTER_QUP_1 35
#define SM8650_MASTER_QUP_2 36
#define SM8650_MASTER_QUP_3 37
#define SM8650_MASTER_QUP_CORE_0 38
#define SM8650_MASTER_QUP_CORE_1 39
#define SM8650_MASTER_QUP_CORE_2 40
#define SM8650_MASTER_SDCC_2 41
#define SM8650_MASTER_SDCC_4 42
#define SM8650_MASTER_SNOC_SF_MEM_NOC 43
#define SM8650_MASTER_SP 44
#define SM8650_MASTER_SYS_TCU 45
#define SM8650_MASTER_UBWC_P 46
#define SM8650_MASTER_UBWC_P_TCU 47
#define SM8650_MASTER_UFS_MEM 48
#define SM8650_MASTER_USB3_0 49
#define SM8650_MASTER_VIDEO 50
#define SM8650_MASTER_VIDEO_CV_PROC 51
#define SM8650_MASTER_VIDEO_PROC 52
#define SM8650_MASTER_VIDEO_V_PROC 53
#define SM8650_SLAVE_A1NOC_SNOC 54
#define SM8650_SLAVE_A2NOC_SNOC 55
#define SM8650_SLAVE_AHB2PHY_NORTH 56
#define SM8650_SLAVE_AHB2PHY_SOUTH 57
#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58
#define SM8650_SLAVE_AOSS 59
#define SM8650_SLAVE_APPSS 60
#define SM8650_SLAVE_CAMERA_CFG 61
#define SM8650_SLAVE_CDSP_MEM_NOC 62
#define SM8650_SLAVE_CLK_CTL 63
#define SM8650_SLAVE_CNOC_CFG 64
#define SM8650_SLAVE_CNOC_MNOC_CFG 65
#define SM8650_SLAVE_CNOC_MSS 66
#define SM8650_SLAVE_CPR_HMX 67
#define SM8650_SLAVE_CPR_NSPCX 68
#define SM8650_SLAVE_CRYPTO_0_CFG 69
#define SM8650_SLAVE_CX_RDPM 70
#define SM8650_SLAVE_DDRSS_CFG 71
#define SM8650_SLAVE_DISPLAY_CFG 72
#define SM8650_SLAVE_EBI1 73
#define SM8650_SLAVE_GEM_NOC_CNOC 74
#define SM8650_SLAVE_GFX3D_CFG 75
#define SM8650_SLAVE_I2C 76
#define SM8650_SLAVE_I3C_IBI0_CFG 77
#define SM8650_SLAVE_I3C_IBI1_CFG 78
#define SM8650_SLAVE_IMEM 79
#define SM8650_SLAVE_IMEM_CFG 80
#define SM8650_SLAVE_IPA_CFG 81
#define SM8650_SLAVE_IPC_ROUTER_CFG 82
#define SM8650_SLAVE_LLCC 83
#define SM8650_SLAVE_LPASS_GEM_NOC 84
#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85
#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86
#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87
#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88
#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89
#define SM8650_SLAVE_MX_2_RDPM 90
#define SM8650_SLAVE_MX_RDPM 91
#define SM8650_SLAVE_NSP_QTB_CFG 92
#define SM8650_SLAVE_PCIE_0 93
#define SM8650_SLAVE_PCIE_1 94
#define SM8650_SLAVE_PCIE_0_CFG 95
#define SM8650_SLAVE_PCIE_1_CFG 96
#define SM8650_SLAVE_PCIE_ANOC_CFG 97
#define SM8650_SLAVE_PCIE_RSCC 98
#define SM8650_SLAVE_PDM 99
#define SM8650_SLAVE_PRNG 100
#define SM8650_SLAVE_QDSS_CFG 101
#define SM8650_SLAVE_QDSS_STM 102
#define SM8650_SLAVE_QSPI_0 103
#define SM8650_SLAVE_QUP_1 104
#define SM8650_SLAVE_QUP_2 105
#define SM8650_SLAVE_QUP_3 106
#define SM8650_SLAVE_QUP_CORE_0 107
#define SM8650_SLAVE_QUP_CORE_1 108
#define SM8650_SLAVE_QUP_CORE_2 109
#define SM8650_SLAVE_RBCPR_CX_CFG 110
#define SM8650_SLAVE_RBCPR_MMCX_CFG 111
#define SM8650_SLAVE_RBCPR_MXA_CFG 112
#define SM8650_SLAVE_RBCPR_MXC_CFG 113
#define SM8650_SLAVE_SDCC_2 114
#define SM8650_SLAVE_SDCC_4 115
#define SM8650_SLAVE_SERVICE_CNOC 116
#define SM8650_SLAVE_SERVICE_CNOC_CFG 117
#define SM8650_SLAVE_SERVICE_MNOC 118
#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119
#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120
#define SM8650_SLAVE_SPSS_CFG 121
#define SM8650_SLAVE_TCSR 122
#define SM8650_SLAVE_TCU 123
#define SM8650_SLAVE_TLMM 124
#define SM8650_SLAVE_TME_CFG 125
#define SM8650_SLAVE_UFS_MEM_CFG 126
#define SM8650_SLAVE_USB3_0 127
#define SM8650_SLAVE_VENUS_CFG 128
#define SM8650_SLAVE_VSENSE_CTRL_CFG 129
#endif

154
include/dt-bindings/interconnect/qcom,sm8650-rpmh.h Normal file
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@ -0,0 +1,154 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
#define MASTER_QSPI_0 0
#define MASTER_QUP_1 1
#define MASTER_QUP_3 2
#define MASTER_SDCC_4 3
#define MASTER_UFS_MEM 4
#define MASTER_USB3_0 5
#define SLAVE_A1NOC_SNOC 6
#define MASTER_QDSS_BAM 0
#define MASTER_QUP_2 1
#define MASTER_CRYPTO 2
#define MASTER_IPA 3
#define MASTER_SP 4
#define MASTER_QDSS_ETR 5
#define MASTER_QDSS_ETR_1 6
#define MASTER_SDCC_2 7
#define SLAVE_A2NOC_SNOC 8
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define MASTER_QUP_CORE_2 2
#define SLAVE_QUP_CORE_0 3
#define SLAVE_QUP_CORE_1 4
#define SLAVE_QUP_CORE_2 5
#define MASTER_CNOC_CFG 0
#define SLAVE_AHB2PHY_SOUTH 1
#define SLAVE_AHB2PHY_NORTH 2
#define SLAVE_CAMERA_CFG 3
#define SLAVE_CLK_CTL 4
#define SLAVE_RBCPR_CX_CFG 5
#define SLAVE_CPR_HMX 6
#define SLAVE_RBCPR_MMCX_CFG 7
#define SLAVE_RBCPR_MXA_CFG 8
#define SLAVE_RBCPR_MXC_CFG 9
#define SLAVE_CPR_NSPCX 10
#define SLAVE_CRYPTO_0_CFG 11
#define SLAVE_CX_RDPM 12
#define SLAVE_DISPLAY_CFG 13
#define SLAVE_GFX3D_CFG 14
#define SLAVE_I2C 15
#define SLAVE_I3C_IBI0_CFG 16
#define SLAVE_I3C_IBI1_CFG 17
#define SLAVE_IMEM_CFG 18
#define SLAVE_CNOC_MSS 19
#define SLAVE_MX_2_RDPM 20
#define SLAVE_MX_RDPM 21
#define SLAVE_PCIE_0_CFG 22
#define SLAVE_PCIE_1_CFG 23
#define SLAVE_PCIE_RSCC 24
#define SLAVE_PDM 25
#define SLAVE_PRNG 26
#define SLAVE_QDSS_CFG 27
#define SLAVE_QSPI_0 28
#define SLAVE_QUP_3 29
#define SLAVE_QUP_1 30
#define SLAVE_QUP_2 31
#define SLAVE_SDCC_2 32
#define SLAVE_SDCC_4 33
#define SLAVE_SPSS_CFG 34
#define SLAVE_TCSR 35
#define SLAVE_TLMM 36
#define SLAVE_UFS_MEM_CFG 37
#define SLAVE_USB3_0 38
#define SLAVE_VENUS_CFG 39
#define SLAVE_VSENSE_CTRL_CFG 40
#define SLAVE_CNOC_MNOC_CFG 41
#define SLAVE_NSP_QTB_CFG 42
#define SLAVE_PCIE_ANOC_CFG 43
#define SLAVE_SERVICE_CNOC_CFG 44
#define SLAVE_QDSS_STM 45
#define SLAVE_TCU 46
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AOSS 2
#define SLAVE_IPA_CFG 3
#define SLAVE_IPC_ROUTER_CFG 4
#define SLAVE_TME_CFG 5
#define SLAVE_APPSS 6
#define SLAVE_CNOC_CFG 7
#define SLAVE_DDRSS_CFG 8
#define SLAVE_IMEM 9
#define SLAVE_SERVICE_CNOC 10
#define SLAVE_PCIE_0 11
#define SLAVE_PCIE_1 12
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_UBWC_P_TCU 2
#define MASTER_APPSS_PROC 3
#define MASTER_GFX3D 4
#define MASTER_LPASS_GEM_NOC 5
#define MASTER_MSS_PROC 6
#define MASTER_MNOC_HF_MEM_NOC 7
#define MASTER_MNOC_SF_MEM_NOC 8
#define MASTER_COMPUTE_NOC 9
#define MASTER_ANOC_PCIE_GEM_NOC 10
#define MASTER_SNOC_SF_MEM_NOC 11
#define MASTER_UBWC_P 12
#define MASTER_GIC 13
#define SLAVE_GEM_NOC_CNOC 14
#define SLAVE_LLCC 15
#define SLAVE_MEM_NOC_PCIE_SNOC 16
#define MASTER_LPIAON_NOC 0
#define SLAVE_LPASS_GEM_NOC 1
#define MASTER_LPASS_LPINOC 0
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
#define MASTER_LPASS_PROC 0
#define SLAVE_LPICX_NOC_LPIAON_NOC 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_ICP 1
#define MASTER_CAMNOC_SF 2
#define MASTER_MDP 3
#define MASTER_CDSP_HCP 4
#define MASTER_VIDEO 5
#define MASTER_VIDEO_CV_PROC 6
#define MASTER_VIDEO_PROC 7
#define MASTER_VIDEO_V_PROC 8
#define MASTER_CNOC_MNOC_CFG 9
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_MNOC_SF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_CDSP_PROC 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_PCIE_ANOC_CFG 0
#define MASTER_PCIE_0 1
#define MASTER_PCIE_1 2
#define SLAVE_ANOC_PCIE_GEM_NOC 3
#define SLAVE_SERVICE_PCIE_ANOC 4
#define MASTER_A1NOC_SNOC 0
#define MASTER_A2NOC_SNOC 1
#define SLAVE_SNOC_GEM_NOC_SF 2
#endif