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drm/radeon: merge IGP chip setup and fixup RS400 vs RS480 support
We only support RS480 (AMD based IGP) at the moment not RS400 (Intel based IGP) ones. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
2735977b12
commit
45e519052e
3 changed files with 138 additions and 165 deletions
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@ -103,20 +103,18 @@
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{0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
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{0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
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{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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@ -2,6 +2,7 @@
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/*
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* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
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* Copyright 2007 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@ -40,7 +41,7 @@
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static int radeon_do_cleanup_cp(struct drm_device * dev);
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static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
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@ -49,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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return ret;
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}
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static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
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ret = RADEON_READ(RS480_NB_MC_DATA);
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RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
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return ret;
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}
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static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
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return RADEON_READ(RS690_MC_DATA);
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ret = RADEON_READ(RS690_MC_DATA);
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RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
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return ret;
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}
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static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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return RS690_READ_MCIND(dev_priv, addr);
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else
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return RS480_READ_MCIND(dev_priv, addr);
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}
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u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
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return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
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return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
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else
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return RADEON_READ(RADEON_MC_FB_LOCATION);
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}
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@ -71,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
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static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
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R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
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R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
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else
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RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
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}
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@ -83,11 +104,11 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
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static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
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R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
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R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
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else
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RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
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}
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@ -106,15 +127,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
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return RADEON_READ(RADEON_PCIE_DATA);
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}
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static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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RADEON_WRITE(RS400_NB_MC_INDEX, addr & 0x7f);
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ret = RADEON_READ(RS400_NB_MC_DATA);
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RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f);
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return ret;
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}
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#if RADEON_FIFO_DEBUG
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static void radeon_status(drm_radeon_private_t * dev_priv)
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{
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@ -255,7 +267,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400)) {
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
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DRM_INFO("Loading R300 Microcode\n");
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for (i = 0; i < 256; i++) {
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
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@ -603,115 +615,78 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
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/* Enable or disable IGP GART on the chip */
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static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
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{
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u32 temp, tmp;
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tmp = RADEON_READ(RADEON_AIC_CNTL);
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if (on) {
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DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
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dev_priv->gart_vm_start,
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(long)dev_priv->gart_info.bus_addr,
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dev_priv->gart_size);
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RADEON_WRITE_IGPGART(RS400_MC_MISC_CNTL, RS400_GART_INDEX_REG_EN);
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RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
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RS400_VA_SIZE_32MB));
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RADEON_WRITE_IGPGART(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
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RS400_TLB_ENABLE |
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RS400_GTW_LAC_EN |
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RS400_1LEVEL_GART));
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RADEON_WRITE_IGPGART(RS400_GART_BASE,
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dev_priv->gart_info.bus_addr);
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temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_MODE_CNTL);
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RADEON_WRITE_IGPGART(RS400_AGP_MODE_CNTL, temp);
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RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
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dev_priv->gart_size = 32*1024*1024;
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radeon_write_agp_location(dev_priv,
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(((dev_priv->gart_vm_start - 1 +
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dev_priv->gart_size) & 0xffff0000) |
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(dev_priv->gart_vm_start >> 16)));
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temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
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RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, temp);
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RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
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RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, RS400_GART_CACHE_INVALIDATE);
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RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL);
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RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, 0);
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}
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}
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/* Enable or disable RS690 GART on the chip */
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static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
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{
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u32 temp;
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if (on) {
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DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
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DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
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dev_priv->gart_vm_start,
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(long)dev_priv->gart_info.bus_addr,
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dev_priv->gart_size);
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temp = RS690_READ_MCIND(dev_priv, RS400_MC_MISC_CNTL);
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RS690_WRITE_MCIND(RS400_MC_MISC_CNTL, (RS400_GART_INDEX_REG_EN |
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RS690_BLOCK_GFX_D3_EN));
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temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
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RS690_BLOCK_GFX_D3_EN));
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else
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IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
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RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
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RS400_VA_SIZE_32MB));
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IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
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RS480_VA_SIZE_32MB));
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temp = RS690_READ_MCIND(dev_priv, RS400_GART_FEATURE_ID);
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RS690_WRITE_MCIND(RS400_GART_FEATURE_ID, (RS400_HANG_EN |
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RS400_TLB_ENABLE |
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RS400_GTW_LAC_EN |
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RS400_1LEVEL_GART));
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temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
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IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
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RS480_TLB_ENABLE |
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RS480_GTW_LAC_EN |
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RS480_1LEVEL_GART));
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temp = dev_priv->gart_info.bus_addr & 0xfffff000;
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temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
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RS690_WRITE_MCIND(RS400_GART_BASE, temp);
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IGP_WRITE_MCIND(RS480_GART_BASE, temp);
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temp = RS690_READ_MCIND(dev_priv, RS400_AGP_MODE_CNTL);
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RS690_WRITE_MCIND(RS400_AGP_MODE_CNTL, ((1 << RS400_REQ_TYPE_SNOOP_SHIFT) |
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RS400_REQ_TYPE_SNOOP_DIS));
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temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
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IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
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RS480_REQ_TYPE_SNOOP_DIS));
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RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
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(unsigned int)dev_priv->gart_vm_start);
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RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
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IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
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(unsigned int)dev_priv->gart_vm_start);
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IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
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} else {
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RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
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RADEON_WRITE(RS480_AGP_BASE_2, 0);
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}
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dev_priv->gart_size = 32*1024*1024;
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temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
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0xffff0000) | (dev_priv->gart_vm_start >> 16));
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RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
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radeon_write_agp_location(dev_priv, temp);
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temp = RS690_READ_MCIND(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE);
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RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN |
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RS400_VA_SIZE_32MB));
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temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
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IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
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RS480_VA_SIZE_32MB));
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do {
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temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
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if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
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RS690_MC_GART_CLEAR_DONE)
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temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
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if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
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break;
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DRM_UDELAY(1);
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} while (1);
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RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL,
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RS400_GART_CACHE_INVALIDATE);
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IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
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RS480_GART_CACHE_INVALIDATE);
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do {
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temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL);
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if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
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RS690_MC_GART_CLEAR_DONE)
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temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
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if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
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break;
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DRM_UDELAY(1);
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} while (1);
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RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL, 0);
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IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
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} else {
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RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, 0);
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IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
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}
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}
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@ -749,12 +724,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
|
|||
{
|
||||
u32 tmp;
|
||||
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
|
||||
radeon_set_rs690gart(dev_priv, on);
|
||||
return;
|
||||
}
|
||||
|
||||
if (dev_priv->flags & RADEON_IS_IGPGART) {
|
||||
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
|
||||
(dev_priv->flags & RADEON_IS_IGPGART)) {
|
||||
radeon_set_igpgart(dev_priv, on);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ enum radeon_family {
|
|||
CHIP_RV380,
|
||||
CHIP_R420,
|
||||
CHIP_RV410,
|
||||
CHIP_RS400,
|
||||
CHIP_RS480,
|
||||
CHIP_RS690,
|
||||
CHIP_RV515,
|
||||
CHIP_R520,
|
||||
|
|
@ -459,9 +459,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
#define RADEON_PCIE_TX_GART_END_LO 0x16
|
||||
#define RADEON_PCIE_TX_GART_END_HI 0x17
|
||||
|
||||
#define RS400_NB_MC_INDEX 0x168
|
||||
# define RS400_NB_MC_IND_WR_EN (1 << 8)
|
||||
#define RS400_NB_MC_DATA 0x16c
|
||||
#define RS480_NB_MC_INDEX 0x168
|
||||
# define RS480_NB_MC_IND_WR_EN (1 << 8)
|
||||
#define RS480_NB_MC_DATA 0x16c
|
||||
|
||||
#define RS690_MC_INDEX 0x78
|
||||
# define RS690_MC_INDEX_MASK 0x1ff
|
||||
|
|
@ -470,46 +470,42 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
#define RS690_MC_DATA 0x7c
|
||||
|
||||
/* MC indirect registers */
|
||||
#define RS400_MC_MISC_CNTL 0x18
|
||||
# define RS400_DISABLE_GTW (1 << 1)
|
||||
#define RS480_MC_MISC_CNTL 0x18
|
||||
# define RS480_DISABLE_GTW (1 << 1)
|
||||
/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
|
||||
# define RS400_GART_INDEX_REG_EN (1 << 12)
|
||||
# define RS480_GART_INDEX_REG_EN (1 << 12)
|
||||
# define RS690_BLOCK_GFX_D3_EN (1 << 14)
|
||||
#define RS400_K8_FB_LOCATION 0x1e
|
||||
#define RS400_GART_FEATURE_ID 0x2b
|
||||
# define RS400_HANG_EN (1 << 11)
|
||||
# define RS400_TLB_ENABLE (1 << 18)
|
||||
# define RS400_P2P_ENABLE (1 << 19)
|
||||
# define RS400_GTW_LAC_EN (1 << 25)
|
||||
# define RS400_2LEVEL_GART (0 << 30)
|
||||
# define RS400_1LEVEL_GART (1 << 30)
|
||||
# define RS400_PDC_EN (1 << 31)
|
||||
#define RS400_GART_BASE 0x2c
|
||||
#define RS400_GART_CACHE_CNTRL 0x2e
|
||||
# define RS400_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
|
||||
/* ??? */
|
||||
# define RS690_MC_GART_CLEAR_STATUS (1 << 1)
|
||||
# define RS690_MC_GART_CLEAR_DONE (0 << 1)
|
||||
# define RS690_MC_GART_CLEAR_PENDING (1 << 1)
|
||||
#define RS400_AGP_ADDRESS_SPACE_SIZE 0x38
|
||||
# define RS400_GART_EN (1 << 0)
|
||||
# define RS400_VA_SIZE_32MB (0 << 1)
|
||||
# define RS400_VA_SIZE_64MB (1 << 1)
|
||||
# define RS400_VA_SIZE_128MB (2 << 1)
|
||||
# define RS400_VA_SIZE_256MB (3 << 1)
|
||||
# define RS400_VA_SIZE_512MB (4 << 1)
|
||||
# define RS400_VA_SIZE_1GB (5 << 1)
|
||||
# define RS400_VA_SIZE_2GB (6 << 1)
|
||||
#define RS400_AGP_MODE_CNTL 0x39
|
||||
# define RS400_POST_GART_Q_SIZE (1 << 18)
|
||||
# define RS400_NONGART_SNOOP (1 << 19)
|
||||
# define RS400_AGP_RD_BUF_SIZE (1 << 20)
|
||||
# define RS400_REQ_TYPE_SNOOP_SHIFT 22
|
||||
# define RS400_REQ_TYPE_SNOOP_MASK 0x3
|
||||
# define RS400_REQ_TYPE_SNOOP_DIS (1 << 24)
|
||||
#define RS400_MC_MISC_UMA_CNTL 0x5f
|
||||
#define RS400_MC_MCLK_CNTL 0x7a
|
||||
#define RS400_MC_UMA_DUALCH_CNTL 0x86
|
||||
#define RS480_K8_FB_LOCATION 0x1e
|
||||
#define RS480_GART_FEATURE_ID 0x2b
|
||||
# define RS480_HANG_EN (1 << 11)
|
||||
# define RS480_TLB_ENABLE (1 << 18)
|
||||
# define RS480_P2P_ENABLE (1 << 19)
|
||||
# define RS480_GTW_LAC_EN (1 << 25)
|
||||
# define RS480_2LEVEL_GART (0 << 30)
|
||||
# define RS480_1LEVEL_GART (1 << 30)
|
||||
# define RS480_PDC_EN (1 << 31)
|
||||
#define RS480_GART_BASE 0x2c
|
||||
#define RS480_GART_CACHE_CNTRL 0x2e
|
||||
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
|
||||
#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
|
||||
# define RS480_GART_EN (1 << 0)
|
||||
# define RS480_VA_SIZE_32MB (0 << 1)
|
||||
# define RS480_VA_SIZE_64MB (1 << 1)
|
||||
# define RS480_VA_SIZE_128MB (2 << 1)
|
||||
# define RS480_VA_SIZE_256MB (3 << 1)
|
||||
# define RS480_VA_SIZE_512MB (4 << 1)
|
||||
# define RS480_VA_SIZE_1GB (5 << 1)
|
||||
# define RS480_VA_SIZE_2GB (6 << 1)
|
||||
#define RS480_AGP_MODE_CNTL 0x39
|
||||
# define RS480_POST_GART_Q_SIZE (1 << 18)
|
||||
# define RS480_NONGART_SNOOP (1 << 19)
|
||||
# define RS480_AGP_RD_BUF_SIZE (1 << 20)
|
||||
# define RS480_REQ_TYPE_SNOOP_SHIFT 22
|
||||
# define RS480_REQ_TYPE_SNOOP_MASK 0x3
|
||||
# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
|
||||
#define RS480_MC_MISC_UMA_CNTL 0x5f
|
||||
#define RS480_MC_MCLK_CNTL 0x7a
|
||||
#define RS480_MC_UMA_DUALCH_CNTL 0x86
|
||||
|
||||
#define RS690_MC_FB_LOCATION 0x100
|
||||
#define RS690_MC_AGP_LOCATION 0x101
|
||||
|
|
@ -529,8 +525,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
#define RADEON_MPP_TB_CONFIG 0x01c0
|
||||
#define RADEON_MEM_CNTL 0x0140
|
||||
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
|
||||
#define RADEON_AGP_BASE_2 0x015c
|
||||
#define RS400_AGP_BASE_2 0x0164
|
||||
#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
|
||||
#define RS480_AGP_BASE_2 0x0164
|
||||
#define RADEON_AGP_BASE 0x0170
|
||||
|
||||
#define RADEON_RB3D_COLOROFFSET 0x1c40
|
||||
|
|
@ -1105,14 +1101,6 @@ do { \
|
|||
RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_IGPGART(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE(RS400_NB_MC_INDEX, \
|
||||
((addr) & 0x7f) | RS400_NB_MC_IND_WR_EN); \
|
||||
RADEON_WRITE(RS400_NB_MC_DATA, (val)); \
|
||||
RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_PCIE(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE8(RADEON_PCIE_INDEX, \
|
||||
|
|
@ -1120,12 +1108,20 @@ do { \
|
|||
RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
|
||||
RADEON_WRITE(R520_MC_IND_DATA, (val)); \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0); \
|
||||
} while (0)
|
||||
#define R500_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
|
||||
RADEON_WRITE(R520_MC_IND_DATA, (val)); \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0); \
|
||||
} while (0)
|
||||
|
||||
#define RS480_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE(RS480_NB_MC_INDEX, \
|
||||
((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
|
||||
RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
|
||||
RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define RS690_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
|
|
@ -1134,6 +1130,14 @@ do { \
|
|||
RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
|
||||
} while (0)
|
||||
|
||||
#define IGP_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
|
||||
RS690_WRITE_MCIND(addr, val); \
|
||||
else \
|
||||
RS480_WRITE_MCIND(addr, val); \
|
||||
} while (0)
|
||||
|
||||
#define CP_PACKET0( reg, n ) \
|
||||
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
|
||||
#define CP_PACKET0_TABLE( reg, n ) \
|
||||
|
|
|
|||
Loading…
Reference in a new issue