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arm/arm64: KVM: vgic: Do not save GICH_HCR / ICH_HCR_EL2
The GIC Hypervisor Configuration Register is used to enable the delivery of virtual interupts to a guest, as well as to define in which conditions maintenance interrupts are delivered to the host. This register doesn't contain any information that we need to read back (the EOIcount is utterly useless for us). So let's save ourselves some cycles, and not save it before writing zero to it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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3 changed files with 0 additions and 8 deletions
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@ -412,7 +412,6 @@ vcpu .req r0 @ vcpu pointer always in r0
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add r11, vcpu, #VCPU_VGIC_CPU
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/* Save all interesting registers */
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ldr r3, [r2, #GICH_HCR]
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ldr r4, [r2, #GICH_VMCR]
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ldr r5, [r2, #GICH_MISR]
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ldr r6, [r2, #GICH_EISR0]
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@ -420,7 +419,6 @@ vcpu .req r0 @ vcpu pointer always in r0
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ldr r8, [r2, #GICH_ELRSR0]
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ldr r9, [r2, #GICH_ELRSR1]
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ldr r10, [r2, #GICH_APR]
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ARM_BE8(rev r3, r3 )
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ARM_BE8(rev r4, r4 )
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ARM_BE8(rev r5, r5 )
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ARM_BE8(rev r6, r6 )
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@ -429,7 +427,6 @@ ARM_BE8(rev r8, r8 )
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ARM_BE8(rev r9, r9 )
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ARM_BE8(rev r10, r10 )
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str r3, [r11, #VGIC_V2_CPU_HCR]
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str r4, [r11, #VGIC_V2_CPU_VMCR]
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str r5, [r11, #VGIC_V2_CPU_MISR]
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#ifdef CONFIG_CPU_ENDIAN_BE8
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@ -47,7 +47,6 @@ __save_vgic_v2_state:
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add x3, x0, #VCPU_VGIC_CPU
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/* Save all interesting registers */
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ldr w4, [x2, #GICH_HCR]
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ldr w5, [x2, #GICH_VMCR]
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ldr w6, [x2, #GICH_MISR]
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ldr w7, [x2, #GICH_EISR0]
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@ -55,7 +54,6 @@ __save_vgic_v2_state:
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ldr w9, [x2, #GICH_ELRSR0]
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ldr w10, [x2, #GICH_ELRSR1]
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ldr w11, [x2, #GICH_APR]
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CPU_BE( rev w4, w4 )
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CPU_BE( rev w5, w5 )
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CPU_BE( rev w6, w6 )
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CPU_BE( rev w7, w7 )
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@ -64,7 +62,6 @@ CPU_BE( rev w9, w9 )
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CPU_BE( rev w10, w10 )
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CPU_BE( rev w11, w11 )
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str w4, [x3, #VGIC_V2_CPU_HCR]
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str w5, [x3, #VGIC_V2_CPU_VMCR]
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str w6, [x3, #VGIC_V2_CPU_MISR]
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CPU_LE( str w7, [x3, #VGIC_V2_CPU_EISR] )
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@ -48,13 +48,11 @@
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dsb st
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// Save all interesting registers
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mrs_s x4, ICH_HCR_EL2
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mrs_s x5, ICH_VMCR_EL2
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mrs_s x6, ICH_MISR_EL2
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mrs_s x7, ICH_EISR_EL2
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mrs_s x8, ICH_ELSR_EL2
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str w4, [x3, #VGIC_V3_CPU_HCR]
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str w5, [x3, #VGIC_V3_CPU_VMCR]
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str w6, [x3, #VGIC_V3_CPU_MISR]
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str w7, [x3, #VGIC_V3_CPU_EISR]
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